公开(公告)号：US11251799B2

公开(公告)日：2022-02-15

申请号：US16792301

申请日：2020-02-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chia-Hui Yu ,  Wun-Jian Su ,  Yu-Jung Chiu ,  Chiao-Chieh Yang

IPC: H03L7/107 ,  G06F13/16 ,  G11C16/32

Abstract: A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and calibrating an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal.

公开(公告)号：US20210203334A1

公开(公告)日：2021-07-01

申请号：US16792301

申请日：2020-02-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chia-Hui Yu ,  Wun-Jian Su ,  Yu-Jung Chiu ,  Chiao-Chieh Yang

IPC: H03L7/107 ,  G11C16/32 ,  G06F13/16

Abstract: A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system; generating a jitter signal by the memory storage device; generating a second signal according to the first signal and the jitter signal; performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit; and calibrating an electrical parameter of the phase-locked loop circuit according to a variation of a time difference between the first signal and the third signal.

公开(公告)号：US11139816B2

公开(公告)日：2021-10-05

申请号：US16822025

申请日：2020-03-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Po-Min Cheng ,  Wun-Jian Su ,  Chia-Hui Yu

IPC: H04L7/00 ,  H03L7/08 ,  H03L7/085 ,  G06F1/10 ,  G06F1/08 ,  H03L7/107

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.

公开(公告)号：US20210273642A1

公开(公告)日：2021-09-02

申请号：US16822025

申请日：2020-03-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Po-Min Cheng ,  Wun-Jian Su ,  Chia-Hui Yu

IPC: H03L7/08 ,  H03L7/085 ,  H03L7/107 ,  G06F1/08 ,  G06F1/10

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.