公开(公告)号：US11647623B2

公开(公告)日：2023-05-09

申请号：US17524917

申请日：2021-11-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Tseng-Fu Lu ,  Jeng-Ping Lin

IPC: H01L21/74 ,  H01L23/535 ,  H10B12/00

CPC classification number: H10B12/20 ,  H01L21/743 ,  H01L23/535

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer.

公开(公告)号：US11502075B2

公开(公告)日：2022-11-15

申请号：US17357986

申请日：2021-06-25

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.

公开(公告)号：US11469234B2

公开(公告)日：2022-10-11

申请号：US17098033

申请日：2020-11-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tseng-Fu Lu

IPC: H01L27/108 ,  G11C5/06

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a storage capacitor, an access transistor, and at least one conductive feature for electrically coupling the storage capacitor to the access transistor. The substrate includes at least one isolation feature defining a plurality of active regions, wherein a plurality of impurity regions of the access transistor are in the active region. The storage capacitor is disposed over the substrate, and the conductive feature extends from the storage capacitor and into a portion of the substrate where one of the impurity regions is disposed. As a result, a contact area between the access transistor and the conductive feature is increased, and an operation speed of the compact semiconductor device is increased.

公开(公告)号：US11417744B2

公开(公告)日：2022-08-16

申请号：US17030982

申请日：2020-09-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tseng-Fu Lu

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate comprising a first top surface; an isolation region disposed in the substrate; an active region surrounded by the isolation region; a gate trench disposed in the active region; a first barrier layer disposed on a portion of a sidewall of the gate trench; a first gate material disposed in the gate trench, wherein the first gate material comprises a first member surrounded by the first barrier layer and a second member extending from the first member toward the first top surface; a second barrier layer disposed on the first barrier layer and the first gate material; a second gate material disposed on the second barrier layer; and a gate insulating material disposed on the second gate material.

公开(公告)号：US11107807B1

公开(公告)日：2021-08-31

申请号：US16789754

申请日：2020-02-13

Applicant: Nanya Technology Corporation

Inventor： Fang Wen Liu ,  Tseng-Fu Lu

IPC: H01L27/02 ,  H01L23/00

Abstract: An IC package having a metal die for ESD protection includes: a printed circuit board having power connections and ground connections; a function die; and a metal die adhered unto the function die and electrically insulated from the function die, wherein the metal die comprises a metal layer and a dummy die underlying the metal layer, and the metal layer is electrically coupled to one or more of the power connections and ground connections of the printed circuit board to provide package level electrostatic discharge (ESD) protection; and an encapsulant covering the metal die, the function die and a surface of the printed circuit board supporting the metal die and function die.

公开(公告)号：US10937886B2

公开(公告)日：2021-03-02

申请号：US16297747

申请日：2019-03-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.

公开(公告)号：US10903080B2

公开(公告)日：2021-01-26

申请号：US16107457

申请日：2018-08-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jhen-Yu Tsai ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/265

Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.

公开(公告)号：US10559560B2

公开(公告)日：2020-02-11

申请号：US16229802

申请日：2018-12-21

Applicant: Nanya Technology Corporation

Inventor： Fang-Wen Liu ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L27/02 ,  H01L49/02

Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.

公开(公告)号：US10461191B2

公开(公告)日：2019-10-29

申请号：US16183700

申请日：2018-11-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu ,  Wei-Ming Liao

IPC: H01L21/3065 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L21/762 ,  H01L27/108 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

公开(公告)号：US11502163B2

公开(公告)日：2022-11-15

申请号：US16662008

申请日：2019-10-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Ching-Chia Huang ,  Tseng-Fu Lu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/762 ,  H01L27/108

Abstract: A semiconductor structure includes an active region, an isolation structure, a first gate structure, and a second gate structure. The active region is disposed over a semiconductor substrate and has a first portion, a second portion, and a third portion. The third portion is between the first portion and the second portion. A shape of the first portion is different from a shape of the third portion, in a top view. The isolation structure is disposed over the semiconductor substrate and surrounds the active region. The first gate structure is disposed between the first portion and the third portion of the active region. The second gate structure is disposed between the second portion and the third portion of the active region.