公开(公告)号：US11869626B2

公开(公告)日：2024-01-09

申请号：US17502792

申请日：2021-10-15

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyunyoo Lee

IPC分类号： G11C7/10

CPC分类号： G11C7/1063 ,  G11C7/109 ,  G11C7/1066 ,  G11C7/1093

摘要： Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US11868650B2

公开(公告)日：2024-01-09

申请号：US17662993

申请日：2022-05-11

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4096 ,  G11C2211/4062

摘要： Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first emphasized characteristic and a second memory circuit having a second emphasized characteristic. The first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US11783885B2

公开(公告)日：2023-10-10

申请号：US17513090

申请日：2021-10-28

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee

IPC分类号： G11C11/406 ,  G11C7/10

CPC分类号： G11C11/40615 ,  G11C7/1009 ,  G11C11/40618 ,  G11C11/40622

摘要： Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM), and an associated host device are described. The memory device includes control circuitry that can determine an operational status of the memory device (e.g., whether the memory device is currently performing a self-refresh operation). The control circuitry can also transmit a signal indicative of the operational status to the host device in response to receiving a command directing the memory device to exit a self-refresh mode. The host device can operate based on the signal. The signal may therefore allow the memory device, the host device, or both to manage operations, including whether to send, receive, or process commands and data read/write requests during times that may be associated with self-refresh operations.

公开(公告)号：US11783883B2

公开(公告)日：2023-10-10

申请号：US17459446

申请日：2021-08-27

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee

IPC分类号： G11C11/00 ,  G11C11/406

CPC分类号： G11C11/40615

摘要： Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device and the host device can include control logic that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.

公开(公告)号：US11644985B2

公开(公告)日：2023-05-09

申请号：US16838873

申请日：2020-04-02

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0625 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0238 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

摘要： Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.

公开(公告)号：US20220334986A1

公开(公告)日：2022-10-20

申请号：US17751298

申请日：2022-05-23

申请人： MICRON TECHNOLOGY, INC.

发明人： Kang-Yong Kim ,  Dean Gans

IPC分类号： G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

摘要： Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US11386940B2

公开(公告)日：2022-07-12

申请号：US16875798

申请日：2020-05-15

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C8/18

摘要： Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

公开(公告)号：US20220209998A1

公开(公告)日：2022-06-30

申请号：US17562588

申请日：2021-12-27

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC分类号： H04L25/03 ,  H04L25/49

摘要： Described apparatuses and methods are directed to equalization with pulse-amplitude modulation (PAM) signaling. As bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. Symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (DFE). DFE, however, can be expensive for chip area and power usage. Therefore, instead of applying DFE to all voltage level determination paths in a receiver, DFE can be applied to a subset of such determination paths. With PAM4 signaling, for example, a DFE circuit can be coupled between an output and an input of a middle slicer. In some cases, symbol detection reliability can be maintained even with fewer DFE circuits by compressing a middle eye of the PAM4 signal. The other two eyes thus have additional headroom for expansion. Encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.

公开(公告)号：US11347666B2

公开(公告)日：2022-05-31

申请号：US17032152

申请日：2020-09-25

申请人： MICRON TECHNOLOGY, INC.

发明人： Kang-Yong Kim ,  Dean Gans

IPC分类号： G06F13/16 ,  G06F9/30 ,  G11C7/22 ,  G11C29/02

摘要： Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US20220066655A1

公开(公告)日：2022-03-03

申请号：US17460013

申请日：2021-08-27

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/06

摘要： Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.