公开(公告)号：US20180114779A1

公开(公告)日：2018-04-26

申请号：US15848083

申请日：2017-12-20

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng

IPC: H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L21/52 ,  H01L23/498 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/568 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

公开(公告)号：US09761534B2

公开(公告)日：2017-09-12

申请号：US15162760

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

公开(公告)号：US20170213315A1

公开(公告)日：2017-07-27

申请号：US15242478

申请日：2016-08-19

Applicant: MediaTek Inc.

Inventor： Ying-Chieh Chen ,  I-Hsuan Lu ,  Shih-Chin Lin

IPC: G06T1/60 ,  G06T11/60

CPC classification number: G06T1/60 ,  G06T11/40 ,  G06T11/60

Abstract: A graphics processing unit (GPU) renders graphical objects into a group of pixels and stores the pixels in an on-chip buffer on the same chip as the GPU. Each pixel has an alpha value that indicates transparency of the pixel. The GPU reads the alpha value of each pixel from the on-chip buffer. According to alpha values of the group of pixels, the GPU generates an alpha hint in the system memory for the group of pixels. The alpha hint represents an aggregate of the alpha values of the group of pixels. The GPU then stores the group of pixels into a frame buffer in the system memory.

公开(公告)号：US20170040292A1

公开(公告)日：2017-02-09

申请号：US15162724

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng

IPC: H01L25/065 ,  H01L21/52 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/52 ,  H01L21/568 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A semiconductor package includes a substrate, a first electronic component, a first conductive layer, a first pillar layer and a first package body. The first electronic component is disposed on the substrate. The first pillar layer connects the first conductive layer and the substrate. The first package body encapsulates the first conductive layer, the first pillar layer and the first electronic component. The first conductive layer is embedded in the first package body.

Abstract translation: 半导体封装包括基板，第一电子元件，第一导电层，第一柱层和第一封装体。 第一电子部件设置在基板上。 第一柱层连接第一导电层和衬底。 第一封装体封装第一导电层，第一柱层和第一电子元件。 第一导电层嵌入第一封装体。

公开(公告)号：US20160180539A1

公开(公告)日：2016-06-23

申请号：US14582134

申请日：2014-12-23

Applicant: MediaTek Inc.

Inventor： Ming-Hao Liao ,  Chih-Ching Chen ,  Shih-Chin Lin ,  Hung-Wei Wu

IPC: G06T7/00 ,  G06T15/80 ,  G06T15/00 ,  G06T7/40 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T15/40

Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.

Abstract translation: 提供了具有binning渲染和相关的预深度处理方法的图形处理电路。 首先，接收对应于指定瓦片的第一原语的第一深度数据。 然后，从预Z缓冲器读取对应于指定瓦片的预深度数据。 如果第一深度数据不大于预深度数据，并且第一原语是不透明原语，则用第一深度数据更新预深度数据。 如果第一深度数据不大于预深度数据，并且第一图元是半透明图元，则根据第一深度数据和预深度数据来定义不确定性排序范围，并且更新预深度数据 具有不确定性排序范围。

公开(公告)号：US09252068B2

公开(公告)日：2016-02-02

申请号：US14611364

申请日：2015-02-02

Applicant: MediaTek Inc.

Inventor： Tai-Yu Chen ,  Chung-Fa Lee ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/36 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在间隔物上的非平面形散热层; 形成在所述电路板上的密封剂层，在所述非平面形散热层与所述电路板之间填充空间; 以及形成在电路板的第二表面上的多个焊球。

公开(公告)号：US20150325549A1

公开(公告)日：2015-11-12

申请号：US14273553

申请日：2014-05-09

Applicant: MEDIATEK INC.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L25/065 ,  H01L23/495 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second package has a plurality of pads connected to the pillar bump pins, respectively. A method of forming a package on package (POP) structure includes at least the following steps: providing a first package with a plurality of pillar bump pins; providing a second package with a plurality of pads; and forming the POP structure by connecting the pillar bump pins to the pads.

Abstract translation: 封装（POP）结构包括至少第一封装和第二封装。 第一封装具有多个支柱凸块销。 第二封装分别具有连接到柱形突起销的多个焊盘。 形成封装（POP）结构的方法至少包括以下步骤：提供具有多个柱状突起销的第一封装; 提供具有多个垫的第二包装; 以及通过将柱形凸块销连接到垫来形成POP结构。

公开(公告)号：US09000581B2

公开(公告)日：2015-04-07

申请号：US13896616

申请日：2013-05-17

Applicant: MediaTek Inc.

Inventor： Tai-Yu Chen ,  Chung-Fa Lee ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/36 ,  H01L23/433 ,  H01L23/498

CPC classification number: H01L23/3736 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上，具有第一横截面尺寸; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在电路板上的密封剂层，覆盖半导体芯片并围绕间隔物; 形成在密封剂层和间隔物上的散热层; 以及形成在电路板的第二表面上的多个焊球。

公开(公告)号：US20240386648A1

公开(公告)日：2024-11-21

申请号：US18583884

申请日：2024-02-22

Applicant: MEDIATEK INC.

Inventor： Po-Yu Huang ,  Shih-Chin Lin ,  Ching-Yi Tsai ,  You-Ming Tsao

IPC: G06T15/00

Abstract: A method for performing automatic activation control regarding VRS and associated apparatus are provided. The method applicable to a processing circuit may include: utilizing a rendering classifier to intercept at least one set of original graphic commands on a command path to obtain at least one rendering property, for classifying rendering corresponding to the at least one set of original graphic commands; utilizing the rendering classifier to classify the rendering into at least one predetermined rendering type among multiple predetermined rendering types according to the at least one rendering property, in order to determine at least one shading rate corresponding to the at least one predetermined rendering type for the rendering; and utilizing a shading rate controller to control the processing circuit to selectively activate a VRS function of the processing circuit, for rendering at the at least one shading rate corresponding to the at least one predetermined rendering type.

公开(公告)号：US11854784B2

公开(公告)日：2023-12-26

申请号：US17989498

申请日：2022-11-17

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/13024

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.