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    WAFER-LEVEL CHIP-SIZE PACKAGE WITH REDISTRIBUTION LAYER
    11.
    发明申请
    WAFER-LEVEL CHIP-SIZE PACKAGE WITH REDISTRIBUTION LAYER 审中-公开

    公开(公告)号：US20170263523A1

    公开(公告)日：2017-09-14

    申请号：US15286844

    申请日：2016-10-06

    Applicant: MediaTek Inc.

    Inventor： Yan-Liang JI ,  Ming-Jen HSIUNG

    IPC: H01L23/31 ,  H01L23/00

    Abstract: A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.

    MOS TRANSISTOR STRUCTURE WITH HUMP-FREE EFFECT
    12.
    发明申请
    MOS TRANSISTOR STRUCTURE WITH HUMP-FREE EFFECT 审中-公开
    具有无波纹效应的MOS晶体管结构

    公开(公告)号：US20170033214A1

    公开(公告)日：2017-02-02

    申请号：US15138683

    申请日：2016-04-26

    Applicant: MediaTek Inc.

    Inventor： Cheng Hua LIN ,  Yan-Liang JI

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/78

    Abstract: A MOS transistor structure is provided. The MOS transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto. A gate layer is disposed on the active area of the semiconductor substrate and has a first edge extending across the first and second edges of the active area. A source region having a first conductivity type is in the active area at a side of the first edge of the gate layer and between the first and second edges of the active area. First and second heavily doped regions of a second conductivity type are in the active area adjacent to the first and second edges thereof, respectively, and spaced apart from each other by the source region.

    Abstract translation: 提供了MOS晶体管结构。 MOS晶体管结构包括具有包括第一边缘和与其相对的第二边缘的有源区域的半导体基板。 栅极层设置在半导体衬底的有源区上，并且具有延伸穿过有源区的第一和第二边缘的第一边缘。 具有第一导电类型的源极区域位于栅极层的第一边缘的一侧的有源区域和有源区域的第一和第二边缘之间。 第二导电类型的第一和第二重掺杂区分别位于与其第一和第二边缘相邻的有源区域中，并且彼此间隔开源区。

    MOS DEVICE WITH ISOLATED DRAIN AND METHOD FOR FABRICATING THE SAME
    13.
    发明申请
    MOS DEVICE WITH ISOLATED DRAIN AND METHOD FOR FABRICATING THE SAME 有权
    具有隔离排水的MOS器件及其制造方法

    公开(公告)号：US20150118816A1

    公开(公告)日：2015-04-30

    申请号：US14582626

    申请日：2014-12-24

    Applicant: MediaTek Inc

    Inventor： Puo-Yu CHIANG ,  Yan-Liang JI

    IPC: H01L29/66

    CPC classification number: H01L29/66659 ,  H01L21/266 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7835

    Abstract: A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

    Abstract translation: 一种制造金属氧化物半导体（MOS）器件的方法，执行以下操作：形成嵌入在半导体衬底的一部分中的第一阱区; 在所述半导体衬底上形成第一图案化掩模层; 在由第一图案化掩模层曝光的半导体衬底的两个部分上执行第一离子注入工艺; 去除所述第一图案化掩模层并在所述半导体衬底上形成第二图案化掩模层，暴露所述第三阱区域的一部分; 对由第二图案化掩模层暴露的第三阱区的部分执行第二离子注入工艺; 对由第二图案化掩模层暴露的第三阱区的部分执行第三注入工艺; 在所述第三阱区域的一部分中形成源极区域; 以及在所述第五阱区的一部分中形成漏极区。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20250040234A1

    公开(公告)日：2025-01-30

    申请号：US18754697

    申请日：2024-06-26

    Applicant: MEDIATEK INC.

    Inventor： Je-Min WEN ,  Yan-Liang JI ,  Chun-Cheng HSU ,  Bo-Yu WEI

    IPC: H01L27/06 ,  H01L21/266 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423

    Abstract: A semiconductor device includes a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor on a substrate. The second MOS transistor is electrically connected to the first MOS transistor. The first MOS transistor includes a first gate dielectric layer and a first gate electrode on the first gate dielectric layer. The second MOS transistor includes a second gate dielectric layer and a second gate electrode on the second gate dielectric layer. The second gate electrode includes a first portion of a first conductivity type and second portions of a second conductivity type on opposite sides of the first portion. The width of the first portion is less than half of the total width of the second gate electrode.

    SEMICONDUCTOR DEVICE
    15.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240072044A1

    公开(公告)日：2024-02-29

    申请号：US18359123

    申请日：2023-07-26

    Applicant: MEDIATEK INC.

    Inventor： Cheng-Hua LIN ,  Yan-Liang JI

    IPC: H01L27/07 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10

    CPC classification number: H01L27/0705 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate strip, a source doped region and a body doped region. The substrate has an active region. The gate strip is disposed on the substrate within the active region. The gate strip extends along a first direction. The source doped region is located in the active region and adjacent to a first side of the gate strip along the first direction. The body doped region is located in the active region and adjacent to the first side of the gate strip. The body doped region and the source doped region have opposite conductivity types. The body doped region has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction.

    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION
    17.
    发明申请
    SEMICONDUCTOR DEVICE CAPABLE OF HIGH-VOLTAGE OPERATION 有权
    具有高电压运行功能的半导体器件

    公开(公告)号：US20160351705A1

    公开(公告)日：2016-12-01

    申请号：US15070289

    申请日：2016-03-15

    Applicant: MediaTek Inc.

    Inventor： Cheng Hua LIN ,  Yan-Liang JI

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/665 ,  H01L29/66681

    Abstract: A semiconductor device includes a semiconductor substrate and a first well region formed in the semiconductor substrate. An insulator is formed in and over a portion of the first well region and a second well region is formed in the first well region at a first side of the insulator. A first doped region is formed in the second well region, and a second doped region is formed in the first well region at a second side opposite the first side of the insulator. A gate structure is formed over the insulator, the first well region between the second well region and the insulator, and the second well region. An isolation element is formed in the semiconductor substrate, surrounding the first well region and the second well region. The first and second doped regions are formed with asymmetric configurations from a top view.

    Abstract translation: 半导体器件包括半导体衬底和形成在半导体衬底中的第一阱区。 绝缘体形成在第一阱区的一部分中和上方，并且在绝缘体的第一侧的第一阱区中形成第二阱区。 第一掺杂区形成在第二阱区中，并且第二掺杂区形成在与绝缘体的第一侧相对的第二侧的第一阱区中。 栅极结构形成在绝缘体上，第二阱区域和绝缘体之间的第一阱区域以及第二阱区域。 隔离元件形成在半导体衬底中，围绕第一阱区和第二阱区。 第一和第二掺杂区域从顶视图形成具有不对称构造。

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