公开(公告)号：US20200211949A1

公开(公告)日：2020-07-02

申请号：US16232898

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01P3/06 ,  H01P11/00 ,  G06F1/16

Abstract: Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods. For example, in some embodiments, an integrated circuit (IC) package substrate may include a conductive trace having a first surface and an opposing second surface; a first conductive via in a first dielectric layer, wherein the first conductive via is in contact with the first surface of the conductive trace; and a second conductive via in a second dielectric layer, wherein the second conductive via is in contact with the second surface of the conductive trace, wherein the second dielectric layer is on the first dielectric layer, and wherein the first conductive via, the second conductive via, and the conductive trace have a same width between 0.5 um and 25 um.

公开(公告)号：US20240006292A1

公开(公告)日：2024-01-04

申请号：US17856185

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857

Abstract: Disclosed herein are via-trace-via structures with improved alignment, and related devices and methods. For example, in some embodiments, an integrated circuit (IC) package support may include a conductive structure having an aperture; a conductive via at least partially nested in the aperture in the conductive structure; and a conductive bridge spanning between and in contact with the conductive structure and the conductive via. In some embodiments, the conductive structure is a conductive pad. In some embodiments, the conductive structure is a conductive plane.

公开(公告)号：US11784181B2

公开(公告)日：2023-10-10

申请号：US17580787

申请日：2022-01-21

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid ,  Veronica Aleman Strong ,  Johanna M. Swan

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/24 ,  H01L29/861 ,  H01L29/47 ,  H01L29/872 ,  H01L29/45

CPC classification number: H01L27/0255 ,  H01L23/5286 ,  H01L27/0248 ,  H01L29/24 ,  H01L29/45 ,  H01L29/47 ,  H01L29/8613 ,  H01L29/872

Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

公开(公告)号：US11676918B2

公开(公告)日：2023-06-13

申请号：US17677877

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L21/00 ,  H01L23/60 ,  H01L23/48 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/60 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L27/0248 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US20220102270A1

公开(公告)日：2022-03-31

申请号：US17548728

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/552 ,  H01L23/00 ,  H01L27/02

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.

公开(公告)号：US20210410343A1

公开(公告)日：2021-12-30

申请号：US17468510

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Veronica Aleman Strong ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Feras Eid

IPC: H05K9/00 ,  H01L23/60 ,  H01L21/48 ,  C08G61/12 ,  C08G73/06 ,  C08G85/00

Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.

公开(公告)号：US20210193595A1

公开(公告)日：2021-06-24

申请号：US16721327

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H05K1/18 ,  H01L27/02 ,  H01L23/00 ,  H01L23/498

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.

公开(公告)号：US20210193571A1

公开(公告)日：2021-06-24

申请号：US16724346

申请日：2019-12-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Veronica Aleman Strong

IPC: H01L23/522 ,  H01L23/498 ,  H01L27/02 ,  H01L23/552 ,  H01L23/00 ,  H01L23/528

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.

公开(公告)号：US11749628B2

公开(公告)日：2023-09-05

申请号：US18053869

申请日：2022-11-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Veronica Aleman Strong ,  Shawna M. Lift ,  Brandon M. Rawlings ,  Jagat Shakya ,  Johanna M. Swan ,  David M. Craig ,  Jeremy Alan Streifer ,  Brennen Karl Mueller

IPC: H01L23/00 ,  H01L21/18 ,  B81B7/00

CPC classification number: H01L24/06 ,  B81B7/0006 ,  B81B7/007

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

公开(公告)号：US11621236B2

公开(公告)日：2023-04-04

申请号：US16728278

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Feras Eid ,  Veronica Aleman Strong ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/60 ,  H01L23/34 ,  H01L23/498 ,  H01L23/532 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.