公开(公告)号：US11973143B2

公开(公告)日：2024-04-30

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Benjamin Chu-Kung ,  Subrina Rafique ,  Devin Merrill ,  Ashish Agrawal ,  Harold Kennel ,  Yang Cao ,  Dipanjan Basu ,  Jessica Torres ,  Anand Murthy

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20220415908A1

公开(公告)日：2022-12-29

申请号：US17375540

申请日：2021-07-14

Applicant: Intel Corporation

Inventor： Guangyu Huang ,  Dipanjan Basu ,  Meng-Wei Kuo ,  Randy Koval ,  Henok Mebrahtu ,  Minsheng Wang ,  Jie Li ,  Fei Wang ,  Qun Gao ,  Xingui Zhang ,  Guanjie Li

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

公开(公告)号：US11233148B2

公开(公告)日：2022-01-25

申请号：US16649304

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US11094716B2

公开(公告)日：2021-08-17

申请号：US16649593

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Rishabh Mehandru ,  Seung Hoon Sung

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US10985263B2

公开(公告)日：2021-04-20

申请号：US16465763

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Van H. Le ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Glenn A. Glass ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200266296A1

公开(公告)日：2020-08-20

申请号：US16649304

申请日：2017-11-06

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Harold W. Kennel ,  Dipanjan Basu ,  Ashish Agrawal ,  Glenn A. Glass ,  Tahir Ghani ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20200075727A1

公开(公告)日：2020-03-05

申请号：US16611125

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Dipanjan Basu ,  Seung Hoon Sung ,  Glenn A. Glass ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66

Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.