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    Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device
    13.
    发明授权
    Digital-to-analog converter, digital-to-analog conversion system, electronic system, base station and mobile device 有权

    公开(公告)号：US12028090B2

    公开(公告)日：2024-07-02

    申请号：US17754310

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet ,  Martin Clara ,  Hundo Shin

    IPC: H03M1/66 ,  H03M1/80

    CPC classification number: H03M1/808

    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

    CHANNEL ESTIMATION USING PEAK CANCELLATION
    14.
    发明申请
    CHANNEL ESTIMATION USING PEAK CANCELLATION 审中-公开

    公开(公告)号：US20180287827A1

    公开(公告)日：2018-10-04

    申请号：US15475783

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Kameran Azadet

    IPC: H04L25/02 ,  H04L27/26

    CPC classification number: H04L25/0228 ,  H04B7/0413 ,  H04J13/0062 ,  H04L27/2647

    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.

    CREST FACTOR REDUCTION CANCELLATION PULSE HAVING A REDUCED LENGTH
    18.
    发明公开
    CREST FACTOR REDUCTION CANCELLATION PULSE HAVING A REDUCED LENGTH 审中-公开

    公开(公告)号：US20240007337A1

    公开(公告)日：2024-01-04

    申请号：US17854155

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

    IPC: H04L27/26

    CPC classification number: H04L27/2618 ,  H04L27/262 ,  H04L27/2615 ,  H04B1/0475

    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) technique that utilizes a cancellation pulse signal having a reduced length. The CFR technique may be applied to a signal to be transmitted, which may comprise a composite signal having one or more carrier signals. Each carrier signal of the composite signal may be filtered via a respective channel filter and then recombined to form the signal to be transmitted, on which the CFR operations are then applied. The length of the cancellation pulse signal is less than the number of taps of the channel filter with the largest number of taps. This reduction in cancellation pulse signal length significantly reduces the processing power required to perform the CFR operations while maintaining regulatory emissions compliance.

    Input circuitry for an analog-to-digital converter, receiver, base station and method for operating an input circuitry for an analog-to-digital converter
    20.
    发明授权
    Input circuitry for an analog-to-digital converter, receiver, base station and method for operating an input circuitry for an analog-to-digital converter 有权

    公开(公告)号：US11489536B1

    公开(公告)日：2022-11-01

    申请号：US17358093

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Martin Clara ,  Daniel Gruber ,  Giacomo Cascio ,  Albert Molina

    IPC: H03M1/10 ,  H04B1/12 ,  H04B1/48

    Abstract: Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

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