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    DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP
    11.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP 有权
    动态随机访问存储器单元与自对准的条纹

    公开(公告)号：US20150206884A1

    公开(公告)日：2015-07-23

    申请号：US14158956

    申请日：2014-01-20

    Applicant: International Business Machines Corporation

    Inventor： John E. Barth, Jr. ,  Kangguo Cheng ,  Herbert L. Ho ,  Ali Khakifirooz ,  Ravikumar Ramachandran ,  Kern Rim ,  Reinaldo A. Vega

    IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/417

    CPC classification number: H01L27/10867 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10879 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66181 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/785

    Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

    Abstract translation: 在形成用于存取晶体管的沟槽电容器以及源极和漏极区域和栅极结构之后，在每个源极区域的第一侧壁上形成介电隔离物，同时物理地暴露每个源极区域的第二侧壁和漏极区域的侧壁。 在去除沟槽顶部电介质部分期间，可以使用每个电介质间隔物作为蚀刻掩模，以形成用于形成带状结构的带状空腔。 可选地，可以进行半导体材料的选择性沉积以形成凸起的源极和漏极区域。 在这种情况下，升高的源极区域仅从第一侧壁生长并且不从第二侧壁生长。 凸起的源极区域可以在形成带状空腔期间用作蚀刻掩模的一部分。 带状结构形成为通过电介质间隔物与相邻的存取晶体管电隔离的自对准结构。

    Self-aligned contacts for high k/metal gate process flow
    13.
    发明授权
    Self-aligned contacts for high k/metal gate process flow 有权
    用于高k /金属栅极工艺流程的自对准触点

    公开(公告)号：US09059134B2

    公开(公告)日：2015-06-16

    申请号：US13791520

    申请日：2013-03-08

    Applicant: International Business Machines Corporation

    Inventor： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

    IPC: H01L21/3205 ,  H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

    Abstract: A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located thereon. Each gate stack includes a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks.

    Abstract translation: 提供一种半导体结构，其包括具有位于其上的多个栅极叠层的半导体衬底。 每个栅极堆叠包括高k栅介质层，功函数金属层和导电金属。 间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。 每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。 接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。 该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。

    Semiconductor fin isolation by a well trapping fin portion
    15.
    发明授权
    Semiconductor fin isolation by a well trapping fin portion 有权
    通过捕获翅片部分的半导体翅片隔离

    公开(公告)号：US08933528B2

    公开(公告)日：2015-01-13

    申请号：US13792797

    申请日：2013-03-11

    Applicant: International Business Machines Corporation

    Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

    Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

    Abstract translation: 提供了包括第一半导体材料的体半导体衬底。 包括第二半导体材料和掺杂剂的阱捕获层形成在体半导体衬底的顶表面上。 阱阱捕获层内的第二半导体材料和掺杂剂的组合被选择为使得掺杂剂的扩散受限于阱捕获层内。 包括第三半导体材料的器件半导体材料层可以在阱捕获层的顶表面上外延生长。 图案化器件半导体材料层，阱捕获层和体半导体衬底的上部以形成至少一个半导体鳍。 形成在每个半导体鳍片中的半导体器件可以通过阱捕获层的其余部分与体半导体衬底电隔离。

    SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION
    17.
    发明申请
    SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION 有权
    半导体熔融分离由一个良好的捕捉FIN部分

    公开(公告)号：US20140252479A1

    公开(公告)日：2014-09-11

    申请号：US13792797

    申请日：2013-03-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Huiling Shang ,  Reinaldo A. Vega

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

    Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.

    Abstract translation: 提供了包括第一半导体材料的体半导体衬底。 包括第二半导体材料和掺杂剂的阱捕获层形成在体半导体衬底的顶表面上。 选择阱捕获层内的第二半导体材料和掺杂剂的组合，使得掺杂剂的扩散限制在阱捕获层内。 包括第三半导体材料的器件半导体材料层可以在阱捕获层的顶表面上外延生长。 图案化器件半导体材料层，阱捕获层和体半导体衬底的上部以形成至少一个半导体鳍。 形成在每个半导体鳍片中的半导体器件可以通过阱捕获层的其余部分与体半导体衬底电隔离。

    SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE
    18.
    发明申请
    SILICON-GERMANIUM FINS AND SILICON FINS ON A BULK SUBSTRATE 有权
    大理石基体上的硅 - 锗元素和硅氧体

    公开(公告)号：US20140252413A1

    公开(公告)日：2014-09-11

    申请号：US13792291

    申请日：2013-03-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Henry K. Utomo ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Myung-Hee Na ,  Ravikumar Ramachandran ,  Huiling Shang

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795

    Abstract: A first silicon-germanium alloy layer is formed on a semiconductor substrate including silicon. A stack of a first silicon layer and a second silicon-germanium alloy layer is formed over a first region of the first silicon-germanium alloy layer, and a second silicon layer thicker than the first silicon layer is formed over a second region of the first silicon-germanium alloy layer. At least one first semiconductor fin is formed in the first region, and at least one second semiconductor fin is formed in the second region. Remaining portions of the first silicon layer are removed to provide at least one silicon-germanium alloy fin in the first region, while at least one silicon fin is provided in the second region. Fin field effect transistors can be formed on the at least one silicon-germanium alloy fin and the at least one silicon fin.

    Abstract translation: 在包括硅的半导体衬底上形成第一硅锗合金层。 在第一硅 - 锗合金层的第一区域上形成第一硅层和第二硅 - 锗合金层的堆叠，并且在第一硅 - 锗合金层的第二区域上形成比第一硅层厚的第二硅层 硅锗合金层。 在第一区域中形成至少一个第一半导体鳍片，并且在第二区域中形成至少一个第二半导体鳍片。 去除第一硅层的剩余部分以在第一区域中提供至少一个硅 - 锗合金翅片，而在第二区域中提供至少一个硅片。 鳍状场效应晶体管可以形成在至少一个硅 - 锗合金翅片和至少一个硅片上。

    UNIFORM FINFET GATE HEIGHT
    20.
    发明申请
    UNIFORM FINFET GATE HEIGHT 有权
    均匀FINFET门高度

    公开(公告)号：US20140151772A1

    公开(公告)日：2014-06-05

    申请号：US13689924

    申请日：2012-11-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： William Cote ,  Johnathan E. Faltermeier ,  Babar A. Khan ,  Ravikumar Ramachandran ,  Theodorus E. Standaert ,  Xinhui Wang

    IPC: H01L29/94 ,  H01L29/66

    CPC classification number: H01L29/945 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66181 ,  H01L29/66545

    Abstract: A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen.

    Abstract translation: 一种方法，包括提供从半导体衬底蚀刻并被氧化物层和氮化物层覆盖的散热片，所述氧化物层位于所述散热片和所述氮化物层之间，去除所述翅片的一部分以形成开口，形成介电隔离物 开口的侧壁，并用填充材料填充开口，其中填充材料的顶表面基本上与氮化物层的顶表面齐平。 该方法还可以包括形成与其中一个鳍片成直角的深沟槽电容器，去除氮化物层以在散热片和填充材料之间形成间隙，其中填充材料具有在间隙上延伸的重新排列的几何形状，以及 去除重入的几何形状并使翅片和填充材料之间的间隙变宽。

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