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公开(公告)号：US20170237549A1
公开(公告)日：2017-08-17
申请号：US15586619
申请日：2017-05-04
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US20170093556A1
公开(公告)日：2017-03-30
申请号：US14868834
申请日：2015-09-29
Applicant: Intel IP Corporation
Inventor： Ofir Degani , Rotem Banin , Sebastian Sievert
CPC classification number: H04L7/002 , H03F3/2178 , H03F3/245 , H03M1/68 , H03M1/82 , H04L7/0091 , H04L27/365
Abstract: Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.
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13.发明授权公开(公告)号：US09571107B2
公开(公告)日：2017-02-14
申请号：US14317435
申请日：2014-06-27
Applicant: Intel IP Corporation
Inventor： Rotem Banin , Elan Banin , Ofir Degani
CPC classification number: H03L7/085 , H03L7/16 , H03L2207/50 , H03M7/3004 , H04B1/40
Abstract: Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
Abstract translation: 这里描述的是与无分频数字锁相环（DPLL）的实现相关的技术，其包括与较高阶Σ-Δ匹配的环路响应。
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14.发明授权Dual digital to time converter (DTC) based differential correlated double sampling DTC calibration 有权双数字到时间转换器（DTC）的差分相关双采样DTC校准公开(公告)号：US09520890B1
公开(公告)日：2016-12-13
申请号：US14998238
申请日：2015-12-23
Applicant: Intel IP Corporation
Inventor： Assaf Ben-Bassat , Ashoke Ravi , Ofir Degani
CPC classification number: H03M1/1014 , H03M1/82
Abstract: A system for calibrating a digital to time converter (DTC), includes a first DTC configured to receive a first digital input code and generate a first DTC output signal, and a second DTC configured to receive a second digital input code and generate a second DTC output signal. Further, the system includes a delay circuit configured to apply a first delay to the first DTC output signal to generate a first delayed DTC output signal and a phase detector circuit configured to determine a phase difference between the first delayed DTC output signal and the second DTC output signal, thereby generating a phase detector output. In addition, the system includes a calibration circuit configured to adjust the first digital input code of the first DTC to an adjusted first code that minimizes the phase detector output, based on a search algorithm.
Abstract translation: 一种用于校准数字到时间转换器（DTC）的系统，包括被配置为接收第一数字输入代码并产生第一DTC输出信号的第一DTC，以及被配置为接收第二数字输入代码并生成第二DTC的第二DTC 输出信号。 此外，该系统包括延迟电路，该延迟电路被配置为对第一DTC输出信号施加第一延迟以产生第一延迟DTC输出信号，以及相位检测器电路，其被配置为确定第一延迟DTC输出信号和第二DTC输出信号之间的相位差 输出信号，从而产生相位检测器输出。 此外，该系统包括校准电路，其被配置为基于搜索算法将第一DTC的第一数字输入码调整到最小化相位检测器输出的经调整的第一代码。
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15.发明授权Digital-to-time converter and methods for generating phase-modulated signals 有权数字时间转换器和用于产生相位调制信号的方法公开(公告)号：US09071304B2
公开(公告)日：2015-06-30
申请号：US13969132
申请日：2013-08-16
Applicant: Intel IP Corporation
Inventor： Rotem Banin , Ofir Degani , Markus Schimper , Ashoke Ravi
CPC classification number: H04B1/0475 , H03F1/02 , H03F3/24 , H03M1/66 , H03M1/86 , H04B2001/045
Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/−1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.
Abstract translation: 数字 - 时间转换器（DTC）的实施例以及用于产生相位调制信号的方法在这里通常被描述。 在一些实施例中，对振荡器信号进行2N +/- 1次除法产生第一和第二除法器信号，对第一分频器信号进行采样以提供上升沿相关信号，对分频器单元输出信号进行采样以提供下降沿 并且第二除法器信号或第二除法器信号的延迟版本被提供作为除法器单元输出信号。 上升沿和下降沿相关信号之间的选择产生边沿信号。 基于第一和第二边缘信号之间的边缘内插产生精细的相位调制输出信号。
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Patent Agency Ranking
16.发明授权公开(公告)号：US11290065B2
公开(公告)日：2022-03-29
申请号：US16650882
申请日：2017-12-29
Applicant: Intel IP Corporation
Inventor： Ali Azam , Ashoke Ravi , Bassam Khamaisi , Ofir Degani
Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.
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公开(公告)号：US11245403B2
公开(公告)日：2022-02-08
申请号：US16618427
申请日：2017-07-17
Applicant: INTEL IP CORPORATION
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi
Abstract: A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.
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公开(公告)号：US10516563B2
公开(公告)日：2019-12-24
申请号：US15753551
申请日：2015-09-25
Applicant: Intel IP Corporation
Inventor： Sebastian Sievert , Ofir Degani , Ashoke Ravi , Rotem Banin
Abstract: An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.
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公开(公告)号：US09660798B2
公开(公告)日：2017-05-23
申请号：US14997056
申请日：2016-01-15
Applicant: Intel IP Corporation
Inventor： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
IPC: H04L27/36 , H04L27/12 , H04L7/033 , H04B7/06 , H04L27/20 , H04W88/06 , H03L7/16 , H04B7/0413 , H04L27/152 , H03K5/00
CPC classification number: H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
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公开(公告)号：US09577684B1
公开(公告)日：2017-02-21
申请号：US14952903
申请日：2015-11-25
Applicant: Intel IP Corporation
Inventor： Sarit Zur , Ofir Degani , Rotem Banin , Assaf Ben-Bassat
CPC classification number: H04B1/0475 , H03C5/00 , H03F1/02 , H03F3/24 , H04B2001/045 , H04L27/361
Abstract: Described herein are technologies related to an implementation of a time interleaved digital-to-time converter (DTC) topology to generate high frequency phase modulated local oscillator (LO) signals. A first and second DTC are connected to an oscillator where outputs of the two DTCs are combined to generate a phase modulated signal and the two DTCs have a frequency rate that is half the frequency rate of the phase modulated signal. The two DTCs can operate at a 50 percent or lower duty cycle.
Abstract translation: 这里描述的是与时间交错数字 - 时间转换器（DTC）拓扑的实施相关的技术，以产生高频相位调制的本地振荡器（LO）信号。 第一和第二DTC连接到振荡器，其中两个DTC的输出被组合以产生相位调制信号，并且两个DTC的频率是相位调制信号的频率的一半。 两个DTC可以在50％或更低的占空比下工作。
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