公开(公告)号：US09197258B1

公开(公告)日：2015-11-24

申请号：US14303945

申请日：2014-06-13

申请人： Intel IP Corporation

发明人： Andreas Menkhoff ,  Michael Bruennert ,  Markus Schimper

IPC分类号： H04B1/04 ,  H04L27/20

CPC分类号： H04B1/0475 ,  H04L27/20 ,  H04L27/361

摘要： A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.

摘要翻译： 调制器和相关联的方法包括被配置为接收调制基带信号的多个数字样本的计算块，并且确定与调制基带信号的预定相位相关联的时间实例。 调制器还包括转换器电路，其被配置为产生具有与所确定的时间实例相关联的上升沿和下降沿的数据相关时钟信号，以及数模转换器，被配置为接收依赖于数据的时钟信号并产生具有转换的方波输出信号 与产生的数据相关时钟信号相关联的时间。

公开(公告)号：US20150365113A1

公开(公告)日：2015-12-17

申请号：US14303945

申请日：2014-06-13

申请人： Intel IP Corporation

发明人： Andreas Menkhoff ,  Michael Bruennert ,  Markus Schimper

IPC分类号： H04B1/04 ,  H04L27/20

CPC分类号： H04B1/0475 ,  H04L27/20 ,  H04L27/361

摘要： A modulator and associated method includes a calculation block configured to receive a plurality of digital samples of a modulated baseband signal, and determine time instances associated with predetermined phase crossings of the modulated baseband signal. The modulator further includes a converter circuit configured to generate a data dependent clock signal having rising and falling edges associated with the determined time instances, and a digital to analog converter configured to receive the data dependent clock signal and generate a square wave output signal having transition times associated with the generated data dependent clock signal.

摘要翻译： 调制器和相关联的方法包括被配置为接收调制基带信号的多个数字样本的计算块，并且确定与调制基带信号的预定相位相关联的时间实例。 调制器还包括转换器电路，其被配置为产生具有与所确定的时间实例相关联的上升沿和下降沿的数据相关时钟信号，以及数模转换器，被配置为接收依赖于数据的时钟信号并产生具有转换的方波输出信号 与产生的数据相关时钟信号相关联的时间。

公开(公告)号：US09071304B2

公开(公告)日：2015-06-30

申请号：US13969132

申请日：2013-08-16

申请人： Intel IP Corporation

发明人： Rotem Banin ,  Ofir Degani ,  Markus Schimper ,  Ashoke Ravi

IPC分类号： H04B1/04 ,  H03M1/66

CPC分类号： H04B1/0475 ,  H03F1/02 ,  H03F3/24 ,  H03M1/66 ,  H03M1/86 ,  H04B2001/045

摘要： Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/−1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.

摘要翻译： 数字 - 时间转换器（DTC）的实施例以及用于产生相位调制信号的方法在这里通常被描述。 在一些实施例中，对振荡器信号进行2N +/- 1次除法产生第一和第二除法器信号，对第一分频器信号进行采样以提供上升沿相关信号，对分频器单元输出信号进行采样以提供下降沿 并且第二除法器信号或第二除法器信号的延迟版本被提供作为除法器单元输出信号。 上升沿和下降沿相关信号之间的选择产生边沿信号。 基于第一和第二边缘信号之间的边缘内插产生精细的相位调制输出信号。