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公开(公告)号：US20180292895A1
公开(公告)日：2018-10-11
申请号：US15483442
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Travis T. Schluessler , Joydeep Ray , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Jefferson Amstutz , Carson Brownlee , Vivek Tiwari , Sayan Lahiri , Kai Xiao , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Deepak S. Vembar , Ankur N. Shah , Balaji Vembu , Josh B. Mastronarde
Abstract: An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.
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公开(公告)号：US20170269136A1
公开(公告)日：2017-09-21
申请号：US15459248
申请日：2017-03-15
Applicant: Intel Corporation
Inventor： Xiaoning Ye , Kai Xiao
IPC: G01R27/28
CPC classification number: G01R27/28
Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.
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公开(公告)号：US20170168528A1
公开(公告)日：2017-06-15
申请号：US14968698
申请日：2015-12-14
Applicant: Intel Corporation
Inventor： Gong Ouyang , Kai Xiao , Lu-Vong Phan
CPC classification number: G06F1/185 , G06F1/1616 , G06F1/1637 , G06F1/1681 , H05K1/029 , H05K1/181 , H05K3/222 , H05K2201/10159 , Y02P70/611
Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
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公开(公告)号：US09485854B2
公开(公告)日：2016-11-01
申请号：US14464279
申请日：2014-08-20
Applicant: Intel Corporation
Inventor： Shaowu Huang , Kai Xiao , Beom-Taek Lee , Boping Wu , Xiaoning Ye
IPC: H05K1/02 , H01P3/08 , H01P11/00 , H05K1/09 , H05K3/30 , H05K1/18 , G06F1/16 , H01P1/26 , H01P5/16 , H04L25/03
CPC classification number: H05K1/023 , G06F1/16 , H01P1/268 , H01P3/08 , H01P5/16 , H01P11/003 , H01R12/737 , H01R13/6461 , H04L25/03006 , H05K1/0216 , H05K1/0231 , H05K1/0243 , H05K1/0246 , H05K1/0268 , H05K1/09 , H05K1/181 , H05K3/22 , H05K3/303 , H05K3/4007 , H05K2201/10159 , H05K2201/10204
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09318850B2
公开(公告)日：2016-04-19
申请号：US14286494
申请日：2014-05-23
Applicant: Intel Corporation
Inventor： Xiang Li , Hao-Han Hsu , Yun Ling , Gong Ouyang , Kai Xiao , Jiangqi He , Lu-Vong T. Phan , Wei Xu
CPC classification number: H01R13/6598 , H01R12/712 , H01R12/721 , H01R12/724 , H01R13/658 , H01R43/18 , H05K3/284 , H05K3/36 , Y10T29/49128
Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，诸如边缘连接器的连接器包括连接器壳体，构造在壳体内的第一组引脚，并且具有耦合到第一电路板的相应信号线的第一端和第二端耦合到相应的信号线 第二电路板的配合连接器以及适于壳体的导电材料，以减少由一个或多个干扰源造成的干扰。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20160057851A1
公开(公告)日：2016-02-25
申请号：US14464279
申请日：2014-08-20
Applicant: Intel Corporation
Inventor： Shaowu Huang , Kai Xiao , Beom-Taek Lee , Boping Wu , Xiaoning Ye
CPC classification number: H05K1/023 , G06F1/16 , H01P1/268 , H01P3/08 , H01P5/16 , H01P11/003 , H01R12/737 , H01R13/6461 , H04L25/03006 , H05K1/0216 , H05K1/0231 , H05K1/0243 , H05K1/0246 , H05K1/0268 , H05K1/09 , H05K1/181 , H05K3/22 , H05K3/303 , H05K3/4007 , H05K2201/10159 , H05K2201/10204
Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20250069182A1
公开(公告)日：2025-02-27
申请号：US18814701
申请日：2024-08-26
Applicant: Intel Corporation
Inventor： Hugues Labbe , Tomer Bar-on , Kai Xiao , Ankur N. Shah , John G. Gierach
Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.
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公开(公告)号：US11990709B2
公开(公告)日：2024-05-21
申请号：US16902832
申请日：2020-06-16
Applicant: Intel Corporation
Inventor： Raul Enriquez Shibayama , Carlos Alberto Lizalde Moreno , Gaudencio Hernandez Sosa , Kai Xiao
IPC: H01R13/00 , H01R12/71 , H01R13/6469 , H01R13/6471 , H05K7/14
CPC classification number: H01R13/6469 , H01R12/718 , H01R13/6471 , H05K7/1452
Abstract: Microelectronic assemblies, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic device having a hexagonal node configuration, wherein the hexagonal node configuration may include a differential signal node pair; a power node; and a plurality of ground nodes; and wherein the differential signal node pair, the power node, and the plurality of ground nodes are arranged in a hexagonal parallelogon pattern, wherein the differential signal node pair includes a first differential signal node adjacent to a second differential signal node, and wherein the power node is adjacent and symmetric to the differential signal node pair; and a microelectronic substrate electrically coupled to the microelectronic device.
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公开(公告)号：US20230318211A1
公开(公告)日：2023-10-05
申请号：US18130404
申请日：2023-04-03
Applicant: Intel Corporation
CPC classification number: H01R12/721 , H01R13/5219 , H01R13/5216 , H01R4/023 , H05K7/20236
Abstract: Methods and apparatus relating to liquid-proof edge connector solutions for immersion cooling are described. In one embodiment, a seal prevents a cooling liquid to cause electrical contact with a pin of an edge card to be inserted in a connector. And, an adhesive prevents the cooling liquid to cause electrical contact with a terminal of the connector. Other embodiments are also claimed and disclosed.
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公开(公告)号：US11762696B2
公开(公告)日：2023-09-19
申请号：US17520583
申请日：2021-11-05
Applicant: Intel Corporation
Inventor： Abhishek R Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
CPC classification number: G06F9/5016 , G06F1/329 , G06F9/4893 , G06F9/5044 , G06T1/20 , G06T1/60 , G06T15/005 , G06T2200/28 , Y02D10/00
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.
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