公开(公告)号：US11854834B2

公开(公告)日：2023-12-26

申请号：US17677105

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11694962B2

公开(公告)日：2023-07-04

申请号：US17229991

申请日：2021-04-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

CPC classification number: H01L23/5385 ,  B81B7/0006 ,  B81B7/007 ,  H01L21/565 ,  H01L23/28 ,  H01L23/5384 ,  H01L23/552

Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.

公开(公告)号：US20230197620A1

公开(公告)日：2023-06-22

申请号：US17558304

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Neelam Prabhu Gaunkar ,  Brandon Rawlings

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49866

Abstract: Methods, systems, apparatus, and articles of manufacture are disclosed for integrated circuit package substrates with high aspect ratio through glass vias. An example microelectronic package including a glass substrate including a via, the via including a high aspect ratio. The example microelectronic package further including a seed layer extending substantially evenly along an inner wall of the via.

公开(公告)号：US11641711B2

公开(公告)日：2023-05-02

申请号：US17695118

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/16 ,  H05K1/02 ,  H05K3/12 ,  H05K3/40 ,  H05K9/00

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11621192B2

公开(公告)日：2023-04-04

申请号：US17338296

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.

公开(公告)号：US20230098957A1

公开(公告)日：2023-03-30

申请号：US17485235

申请日：2021-09-24

Applicant: INTEL CORPORATION

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Adel Elsherbini ,  Henning Braunisch

IPC: H01L23/00

Abstract: A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

公开(公告)号：US20230094979A1

公开(公告)日：2023-03-30

申请号：US17484299

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Adel Elsherbini ,  Stephen Morein ,  Yoshihiro Tomita ,  Thomas L. Sounart ,  Johanna Swan ,  Brandon M. Rawlings

IPC: H01L23/50 ,  H01L23/532

Abstract: Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.

公开(公告)号：US11532574B2

公开(公告)日：2022-12-20

申请号：US16394905

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L21/00 ,  H01L23/66 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/16 ,  H01P3/06 ,  H01P11/00

Abstract: Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US20220399324A1

公开(公告)日：2022-12-15

申请号：US17344348

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Adel A. Elsherbini ,  Kimin Jun ,  Johanna M. Swan ,  Shawna M. Liff ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

公开(公告)号：US11495552B2

公开(公告)日：2022-11-08

申请号：US16024702

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Thomas Sounart ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prithwish Chatterjee ,  Andrew J. Brown

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.