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    Zero-misalignment two-via structures
    2.
    发明授权
    Zero-misalignment two-via structures 有权

    公开(公告)号：US11694951B2

    公开(公告)日：2023-07-04

    申请号：US17537406

    申请日：2021-11-29

    Applicant: Intel Corporation

    Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings ,  Johanna Swan

    IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

    CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5386

    Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

    Interconnection structure fabrication using grayscale lithography
    6.
    发明授权
    Interconnection structure fabrication using grayscale lithography 有权

    公开(公告)号：US11101205B2

    公开(公告)日：2021-08-24

    申请号：US16564168

    申请日：2019-09-09

    Applicant: Intel Corporation

    Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

    IPC: H01L23/498 ,  G03F1/38 ,  G03F1/54 ,  G03F1/68

    Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

    Organic interposers for integrated circuit packages
    7.
    发明授权
    Organic interposers for integrated circuit packages 有权

    公开(公告)号：US10998272B2

    公开(公告)日：2021-05-04

    申请号：US16573943

    申请日：2019-09-17

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

    Abstract: An electronic interposer may be formed using organic material layers, while allowing for the fabrication of high density interconnects within the electronic interposer without the use of embedded silicon bridges. This is achieved by forming the electronic interposer in three sections, i.e. an upper section, a lower section and a middle section. The middle section may be formed between the upper section and the lower section, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section, and wherein conductive routes within the middle section have a higher density than conductive routes within the upper section and the lower section.

    DUAL SIDED THERMAL MANAGEMENT SOLUTIONS FOR INTEGRATED CIRCUIT PACKAGES
    10.
    发明申请
    DUAL SIDED THERMAL MANAGEMENT SOLUTIONS FOR INTEGRATED CIRCUIT PACKAGES 有权

    公开(公告)号：US20210080500A1

    公开(公告)日：2021-03-18

    申请号：US16573946

    申请日：2019-09-17

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

    IPC: G01R31/28 ,  G01K7/42

    Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

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