公开(公告)号：US20150380482A1

公开(公告)日：2015-12-31

申请号：US14658121

申请日：2015-03-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ho Kyun AHN ,  Hae Cheon KIM ,  Jong Won LIM ,  Dong Min KANG ,  Yong Hwan KWON ,  SEONG IL KIM ,  Zin Sig KIM ,  Eun Soo NAM ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Kyung Ho LEE ,  Jong Min LEE ,  Kyu Jun CHO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L21/28 ,  H01L29/49 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/31 ,  H01L29/778 ,  H01L29/45

CPC classification number: H01L21/28264 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.

Abstract translation: 本文提供了包括基板的半导体器件; 形成在所述基板的顶部上的有源层; 形成在所述有源层的顶部上并具有第一孔的保护层; 源电极，形成在保护层顶部的驱动栅电极和漏电极; 以及形成在所述第一孔的顶部上的第一附加栅电极，其中由于施加到所述源电极，漏电极和驱动栅电极中的每一个的电压，向所述有源层，保护层和驱动栅电极施加电场， 并且第一附加栅电极被配置为衰减施加到有源层，保护层和驱动栅电极的至少一部分的电场的尺寸。

公开(公告)号：US20150270822A1

公开(公告)日：2015-09-24

申请号：US14478295

申请日：2014-09-05

Applicant: Electronics and Telecommunications Research Institute

Inventor： Dong Min KANG ,  Seong Il KIM ,  Sang Heung LEE ,  Chull Won JU ,  Ho Kyun AHN ,  Hyung Sup YOON ,  Jong Won LIM

IPC: H03H7/38

CPC classification number: H03H7/38 ,  H01L23/642 ,  H01L2224/49175 ,  H01P1/2039 ,  H01P5/12 ,  H05K1/025 ,  H05K2201/09781

Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.

Abstract translation: 本文提供了一种包括匹配单元及其匹配方法的组件封装，所述匹配单元包括：衬底; 形成在所述基板上的传输线，所述传输线连接到所述部件封装的端子; 电连接所述传输线和中心部件的接合线; 以及具有通过布线连接与传输线电连接的多个电容器的电容器单元，其中匹配单元的电感通过调整接合线的长度而变化，并且匹配单元的电容可通过增加或减小而变化 通过延长或切断布线连接，在电容器单元内的电容器之间电连接到传输线的电容器的数量。

公开(公告)号：US20150194494A1

公开(公告)日：2015-07-09

申请号：US14243322

申请日：2014-04-02

Applicant: Electronics and Telecommunications Research Institute

Inventor： Ho Kyun AHN ,  Hae Cheon KIM ,  Zin Sig KIM ,  Sang Heung LEE ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Dong Min KANG ,  Seong Il KIM ,  Jong Min LEE ,  Jong Won LIM ,  Yong Hwan KWON ,  Eun Soo NAM

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/402 ,  H01L21/283 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/42312 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787

Abstract: Disclosed are a field effect transistor for high voltage driving including a gate electrode structure in which a gate head extended in a direction of a drain is supported by a field plate embedded under a region of the gate head so as to achieve high voltage driving, and a manufacturing method thereof. Accordingly, the gate head extended in the direction of the drain is supported by the field plate electrically spaced by using an insulating layer, so that it is possible to stably manufacture a gate electrode including the extended gate head, and gate resistance is decreased by the gate head extended in the direction of the drain and an electric field peak value between the gate and the drain is decreased by the gate electrode including the gate head extended in the direction of the drain and the field plate proximate to the gate, thereby achieving an effect in that a breakdown voltage of a device is increased.

Abstract translation: 公开了一种用于高电压驱动的场效应晶体管，其包括栅极电极结构，其中在漏极方向上延伸的栅极头由嵌入在栅极头的区域内的场板支撑以实现高电压驱动，以及 其制造方法。 因此，在漏极方向上延伸的栅极头通过使用绝缘层而被电隔离的场板支撑，使得可以稳定地制造包括延伸栅极头的栅电极，并且栅极电阻通过 栅极头在漏极的方向上延伸，栅极和漏极之间的电场峰值由包括在漏极方向上延伸的栅极和靠近栅极的场板的栅电极减小，由此实现 效果是器件的击穿电压增加。

公开(公告)号：US20150144961A1

公开(公告)日：2015-05-28

申请号：US14175452

申请日：2014-02-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hyung Sup YOON ,  Byoung Gue MIN ,  Ho Kyun AHN ,  Jong Won LIM ,  Dong Min KANG ,  Jong Min LEE

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.

Abstract translation: 高频器件包括：形成在外延结构上的覆盖层; 源极和漏极形成在覆盖层上; 形成在所述源电极和漏电极以及所述覆盖层的整个表面上的阶梯形状的多层绝缘图案; 通过所述多层绝缘图案和所述覆盖层与所述外延结构接触的T形栅极; 以及在T形栅极和多层绝缘图案的整个表面上形成的钝化层。

公开(公告)号：US20140363937A1

公开(公告)日：2014-12-11

申请号：US14308000

申请日：2014-06-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woo Jin CHANG ,  Jong-Won LIM ,  Ho Kyun AHN ,  Sang Choon KO ,  Sung Bum BAE ,  Chull Won JU ,  Young Rak PARK ,  Jae Kyoung MUN ,  Eun Soo NAM

IPC: H01L29/66 ,  H01L29/40

CPC classification number: H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。