公开(公告)号：US10528689B1

公开(公告)日：2020-01-07

申请号：US15364049

申请日：2016-11-29

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Vivek Chickermane ,  Dhruv Dua ,  Krishna Vijaya Chakravadhanula

IPC: G06F17/50

Abstract: A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.

公开(公告)号：US10331506B1

公开(公告)日：2019-06-25

申请号：US15639092

申请日：2017-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vivek Chickermane ,  Christos Papameletis ,  Krishna Vijaya Chakravadhanula ,  Brian Edward Foutz

IPC: G01R31/28 ,  G06F11/07 ,  G06F11/30

Abstract: Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.

公开(公告)号：US09817068B1

公开(公告)日：2017-11-14

申请号：US14754386

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Vivek Chickermane ,  Krishna Vijaya Chakravadhanula ,  Brian Edward Foutz ,  Steev Wilcox ,  Paul Alexander Cunningham ,  David George Scott ,  Louis Christopher Milano ,  Dale Edward Meehl

IPC: G01R31/3177 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/31813 ,  G01R31/318335 ,  G01R31/318385 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/31921

Abstract: Systems and methods efficiently bring additional variables into a Pseudo-Random Pattern Generator (“PRPG”) in the early cycles of an automatic test pattern generation (“ATPG”) process without utilizing any additional hardware or control pins. Overscanning (e.g., scanning longer than the length of the longest channel) for some additional cycles brings in enough variables into the PRPG. Data corresponding to earlier cycles of the ATPG process is removed.

公开(公告)号：US09501590B1

公开(公告)日：2016-11-22

申请号：US14639014

申请日：2015-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Paul A. Cunningham ,  Steev Wilcox ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/31704 ,  G01R31/318583

Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

公开(公告)号：US09465896B1

公开(公告)日：2016-10-11

申请号：US14639029

申请日：2015-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Paul A. Cunningham ,  Steev Wilcox ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/44 ,  G01R31/28 ,  G06F17/5045 ,  G06F2217/14

Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Abstract translation: CoDec在设计中用于测试集成电路。 在本文描述的实施例中，CoDec的部分分布在IC的区域上。 特别地，压缩机和解压缩器都可以分布在IC上。 为此，XOR栅极位于芯片区域上的扫描链的本地，以将电线长度减小到输入/输出测试引脚。 压缩机和解压缩器可以分布在二维网格中。 压缩器可以在两个不同的方向上对每个扫描链进行异或，使得故障可以被解回到IC的特定区域。

公开(公告)号：US08732632B1

公开(公告)日：2014-05-20

申请号：US13835871

申请日：2013-03-15

Applicant: Cadence Design Systems, Inc.

Inventor： Brion Keller ,  Pradeep Nagaraj ,  Richard Schoonover ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/31855 ,  G06F2217/14

Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Abstract translation: SOC设计越来越多地使用具有标准封装单元的IP内核，其具有用于内部逻辑的供应商提供的测试模式。 为了测试包装器，互连和其他边界逻辑，在合成或ATPG环境中从设计中提取边界模型。 识别封装单元，并通过包装链的结构跟踪提取边界逻辑，并从核心输入/输出跟踪到包装单元。 创建的边界模型不包括由供应商提供的测试模式测试的核心内部逻辑，以迁移到包含芯片接口。 构建SOC ATPG模型，其中包括所有嵌入式核心，互连以及驻留在SOC顶层级别的任何其他逻辑的边界模型。 该模型对于所有嵌入式核心外部的测试逻辑非常紧凑但精确。 测试时间缩短，测试图形生成大大简化，同时具有良好的测试覆盖率。 同样的方法用于具有多个管芯的3D封装。

公开(公告)号：US12055586B1

公开(公告)日：2024-08-06

申请号：US18113898

申请日：2023-02-24

Applicant: Cadence Design Systems, Inc.

Inventor： Sagar Kumar ,  Rajesh Khurana ,  Vivek Chickermane

IPC: G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/31723 ,  G01R31/318555 ,  G01R31/318597

Abstract: Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.

公开(公告)号：US11256839B1

公开(公告)日：2022-02-22

申请号：US17228282

申请日：2021-04-12

Applicant: Cadence Design Systems, Inc.

Inventor： Vivek Chickermane ,  Subhasish Mukherjee

IPC: G06F30/333 ,  G06F30/347 ,  G06F30/343

Abstract: A scan chain engine can determine a set number of EXTEST scan chains for the IP block and based on a predetermined maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine iteratively executes partitioning on the IP block to generate a set of partitions. Each partition in the set of partitions has a number of EXTEST wrapper cells that does not exceed the maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine selectively merges partitions of the set of partitions to form a set of populated partitions that each include an EXTEST wrapper cell. The number of partitions is equal to the set number of EXTEST scan chains for the IP block. The scan chain engine generates wire paths connecting EXTEST wrapper cells of each populated partition to construct the set number of EXTEST scan chains for the IP block.

公开(公告)号：US10740515B1

公开(公告)日：2020-08-11

申请号：US16224592

申请日：2018-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： Jagjot Kaur ,  Priyanka Dasgupta ,  Vivek Chickermane ,  Gopi Kudva

IPC: G06F17/50 ,  G06F30/30 ,  G01R31/317 ,  G06F30/3323 ,  G06F111/04 ,  G06F111/20

Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

公开(公告)号：US10551435B1

公开(公告)日：2020-02-04

申请号：US15163351

申请日：2016-05-24

Applicant: Cadence Design Systems, Inc.

Inventor： Nitin Parimi ,  Krishna Vijaya Chakravadhanula ,  Patrick Wayne Gallagher ,  Vivek Chickermane ,  Brian Edward Foutz

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  H03K3/012 ,  G01R31/3185 ,  H03K19/096 ,  G01R31/3187 ,  G11C16/32

Abstract: Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.