公开(公告)号：US10740515B1

公开(公告)日：2020-08-11

申请号：US16224592

申请日：2018-12-18

Applicant: Cadence Design Systems, Inc.

Inventor： Jagjot Kaur ,  Priyanka Dasgupta ,  Vivek Chickermane ,  Gopi Kudva

IPC: G06F17/50 ,  G06F30/30 ,  G01R31/317 ,  G06F30/3323 ,  G06F111/04 ,  G06F111/20

Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

公开(公告)号：US10417363B1

公开(公告)日：2019-09-17

申请号：US15391594

申请日：2016-12-27

Applicant: Cadence Design Systems, Inc.

Inventor： Jagjot Kaur ,  Priyanka Dasgupta ,  Pratyush Aditya Kothamasu ,  Vivek Chickermane

IPC: G06F17/50 ,  G06F11/27

Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.