公开(公告)号：US08732632B1

公开(公告)日：2014-05-20

申请号：US13835871

申请日：2013-03-15

Applicant: Cadence Design Systems, Inc.

Inventor： Brion Keller ,  Pradeep Nagaraj ,  Richard Schoonover ,  Vivek Chickermane

IPC: G06F17/50

CPC classification number: G01R31/31855 ,  G06F2217/14

Abstract: SOC designs increasingly feature IP cores with standardized wrapper cells having vendor-provided test patterns for the internal logic. To test wrapper, interconnect, and other boundary logic, a boundary model is extracted from the design in a synthesis or ATPG environment. Wrapper cells are identified and boundary logic extracted by structural tracing of wrapper chains and tracing from core inputs/outputs to the wrapper cells. A created boundary model excludes core internal logic tested by vendor-provided test patterns to be migrated to the containing chip interface. An SOC ATPG model is built including boundary models for all embedded cores, interconnects, and any other logic residing at the SOC top hierarchical level. This model is very compact yet accurate for testing logic external to all embedded cores. Test time is reduced and test pattern generation greatly simplified, while featuring good test coverage. The same approach is used for 3D packages having multiple dies.

Abstract translation: SOC设计越来越多地使用具有标准封装单元的IP内核，其具有用于内部逻辑的供应商提供的测试模式。 为了测试包装器，互连和其他边界逻辑，在合成或ATPG环境中从设计中提取边界模型。 识别封装单元，并通过包装链的结构跟踪提取边界逻辑，并从核心输入/输出跟踪到包装单元。 创建的边界模型不包括由供应商提供的测试模式测试的核心内部逻辑，以迁移到包含芯片接口。 构建SOC ATPG模型，其中包括所有嵌入式核心，互连以及驻留在SOC顶层级别的任何其他逻辑的边界模型。 该模型对于所有嵌入式核心外部的测试逻辑非常紧凑但精确。 测试时间缩短，测试图形生成大大简化，同时具有良好的测试覆盖率。 同样的方法用于具有多个管芯的3D封装。