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    Forming a semiconductor device having epitaxially grown source and drain regions
    12.
    发明授权
    Forming a semiconductor device having epitaxially grown source and drain regions 有权
    形成具有外延生长的源区和漏区的半导体器件

    公开(公告)号：US07795089B2

    公开(公告)日：2010-09-14

    申请号：US11680219

    申请日：2007-02-28

    Applicant: Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

    Inventor： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

    IPC: H01L21/8238

    CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772

    Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

    Abstract translation: 在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。 第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。 在第一和第二区域上形成第一绝缘层。 第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。 从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。 半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。 在凹部中外延生长半导体材料。 去除第一绝缘层的剩余部分。

    Method of manufacturing DRAM cell
    13.
    发明授权
    Method of manufacturing DRAM cell 失效
    制造DRAM单元的方法

    公开(公告)号：US5068200A

    公开(公告)日：1991-11-26

    申请号：US490326

    申请日：1990-03-08

    Applicant: Laegu Kang ,  Kyungtae Kim

    Inventor： Laegu Kang ,  Kyungtae Kim

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

    CPC classification number: H01L27/10852 ,  H01L27/10808

    Abstract: This invention relates to a method of manufacturing a DRAM cell which has a stacked capacitor and forming drain and source polycrystalline silicon regions on surface of a semiconductor substrate. The invention is directed to: a first step for forming a field oxide film and channel stopper as well as a polycrystalline silicon oxide film doped with impurities; a second step for dividing said silicon into a drain and source polycrystalline silicon region and forming a gate oxide film between the two silicon regions simultaneously with the drain and source diffusion regions and a gate electrode on the gate nitride film; a third step for forming an insulating film on the upper surface of the nitride film and a window on the source polycrystalline silicon region, a storage poly contacting with the same through the window; a fourth step for forming a dielectric layer and a plate poly of the stacked capacitor; and a fifth step forming another insulating film thereon and forming a window on the drain polycrystalline silicon region and also forming a bit line contacting with the exposed drain polycrystalline silicon region through that window. This invention can prevent the generation of leakage current resulting from the damage caused by the drain and source diffusion polycrystalline silicon regions when an etching process is used for the formation of the storage poly and the bit line.

    Abstract translation: 本发明涉及一种具有堆叠电容器并在半导体衬底的表面上形成漏极和源极多晶硅区域的DRAM单元的制造方法。 本发明涉及：形成场氧化物膜和通道阻挡物的第一步骤以及掺杂有杂质的多晶氧化硅膜; 将所述硅分成漏极和源极多晶硅区域并在所述两个硅区域之间与所述漏极和源极扩散区域同时形成栅极氧化膜以及所述栅极氮化物膜上的栅电极的第二步骤; 用于在氮化物膜的上表面上形成绝缘膜的第三步骤和源多晶硅区域上的窗口，通过窗口与其接触的储存器; 用于形成叠层电容器的电介质层和板状多晶硅的第四步骤; 以及在其上形成另一绝缘膜并在漏极多晶硅区域上形成窗口的第五步骤，并且还形成通过该窗口与暴露的漏极多晶硅区域接触的位线。 本发明可以防止当使用蚀刻工艺形成存储多晶硅和位线时由漏极和源极扩散多晶硅区域引起的损坏产生漏电流。

    High pressure deuterium treatment for semiconductor/high-K insulator interface
    16.
    发明授权
    High pressure deuterium treatment for semiconductor/high-K insulator interface 有权
    用于半导体/高K绝缘子接口的高压氘处理

    公开(公告)号：US08445969B2

    公开(公告)日：2013-05-21

    申请号：US13094873

    申请日：2011-04-27

    Applicant: Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

    Inventor： Xiangdong Chen ,  Laegu Kang ,  Weipeng Li ,  Dae-Gyu Park ,  Melanie J. Sherony

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/7843

    Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

    Abstract translation: 集成电路结构在衬底上包括至少一对互补晶体管。 一对互补晶体管包括第一晶体管和第二晶体管。 此外，在第一晶体管和第二晶体管上只有一个应力产生层，并且在第一晶体管和第二晶体管上施加拉伸应变力。 第一晶体管具有第一沟道区，第一沟道区上的栅极绝缘体，以及第一沟道区和栅绝缘体之间的氘区。 第二晶体管具有锗掺杂沟道区以及锗掺杂沟道区上的相同栅极绝缘体以及锗掺杂沟道区和栅绝缘体之间的相同氘区。

    FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS
    18.
    发明申请
    FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS 有权
    形成具有外源性源和漏区的半导体器件

    公开(公告)号：US20080206940A1

    公开(公告)日：2008-08-28

    申请号：US11680219

    申请日：2007-02-28

    Applicant: Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

    Inventor： Laegu Kang ,  Vishal P. Trivedi ,  Da Zhang

    IPC: H01L21/8234

    CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772

    Abstract: A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.

    Abstract translation: 在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。 第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。 在第一和第二区域上形成第一绝缘层。 第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。 从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。 半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。 在凹部中外延生长半导体材料。 去除第一绝缘层的剩余部分。

    METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS
    20.
    发明申请
    METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS 有权
    形成具有更换盖的块状FINFET器件的方法，以减少通过泄漏电流的冲击

    公开(公告)号：US20130224945A1

    公开(公告)日：2013-08-29

    申请号：US13408139

    申请日：2012-02-29

    Applicant: Yanxiang Liu ,  Michael Hargrove ,  Xiaodong Yang ,  Hans Van Meer ,  Laegu Kang ,  Christian Gruensfelder ,  Srikanth Samavedam

    Inventor： Yanxiang Liu ,  Michael Hargrove ,  Xiaodong Yang ,  Hans Van Meer ,  Laegu Kang ,  Christian Gruensfelder ,  Srikanth Samavedam

    IPC: H01L21/28

    CPC classification number: H01L29/66545 ,  H01L29/66795

    Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity.

    Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的沟槽，从而限定用于器件的鳍结构，在每个沟槽内形成局部隔离区，在翅片结构上形成牺牲栅极结构，其中 所述牺牲栅极结构至少包括牺牲栅电极，以及在所述鳍结构之上和所述局部隔离区之上的沟槽内形成绝缘材料层。 在该示例中，该方法还包括执行至少一个蚀刻工艺以去除牺牲栅极结构，从而在去除牺牲栅极结构之后，确定栅极腔，执行至少一个蚀刻工艺以在局部隔离区域中形成凹陷， 以及形成位于局部隔离区域和门腔中的凹部中的替换栅极结构。

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