公开(公告)号：US12183794B2

公开(公告)日：2024-12-31

申请号：US17395854

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/40

Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

公开(公告)号：US12046473B2

公开(公告)日：2024-07-23

申请号：US17358244

申请日：2021-06-25

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Vittoriano Ruscio ,  Wei Zou ,  David J. Lee

IPC: H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L21/265 ,  H01L21/26593 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: Disclosed herein are methods for backside wafer dopant activation using a low-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a low-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

公开(公告)号：US11804537B2

公开(公告)日：2023-10-31

申请号：US17307809

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Hans-Joachim L. Gossmann

IPC: H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66068 ,  H01L21/047 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7813

Abstract: Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

公开(公告)号：US11527637B2

公开(公告)日：2022-12-13

申请号：US17188051

申请日：2021-03-01

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/778

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.

公开(公告)号：US11437488B2

公开(公告)日：2022-09-06

申请号：US17102573

申请日：2020-11-24

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  David J. Lee ,  Jason Appell

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/203 ,  H01L21/8234 ,  H01L29/423

Abstract: Disclosed herein are methods for forming split-gate MOSFETs including a gate shield. In some embodiments, a method may include providing a device structure including a well formed in an epitaxial layer, forming a set of trenches through the well and the epitaxial layer, implanting the device structure to form a gate shield layer at a bottom of each of the set of trenches, and forming a gate spacer layer over the device structure including within the set of trenches.

公开(公告)号：US20220278221A1

公开(公告)日：2022-09-01

申请号：US17188051

申请日：2021-03-01

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/06

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches.

公开(公告)号：US20250081583A1

公开(公告)日：2025-03-06

申请号：US18950957

申请日：2024-11-18

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/40

Abstract: Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

公开(公告)号：US12087585B2

公开(公告)日：2024-09-10

申请号：US17362946

申请日：2021-06-29

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Judy Campbell Soukup

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/26593 ,  H01L21/26533 ,  H01L21/266

Abstract: Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

公开(公告)号：US11798982B2

公开(公告)日：2023-10-24

申请号：US17238504

申请日：2021-04-23

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Samphy Hong ,  Jason Appell ,  David J. Lee

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66 ,  H01L21/76 ,  H01L21/761 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L21/761 ,  H01L21/7602 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: Methods may include providing a device structure including a well formed in an epitaxial layer, and forming a plurality of shielding layers in the device structure, wherein at least one shielding layer is formed between a pair of adjacent sacrificial gates of a plurality of sacrificial gates. The method may further include forming a contact over the at least one shielding layer, forming a fill layer over the contact, and forming a plurality of trenches into the device structure, wherein at least one trench of the plurality of trenches is formed between a pair of adjacent shielding layers of the plurality of shielding layers, and wherein the at least one trench of the plurality of trenches is defined in part by a sidewall of the fill layer. The method may further include forming a gate structure within the at least one trench of the plurality of trenches.

公开(公告)号：US11721743B2

公开(公告)日：2023-08-08

申请号：US17130605

申请日：2020-12-22

Applicant: Applied Materials, Inc.

Inventor： Qintao Zhang ,  Wei Zou ,  Samphy Hong

IPC: H01L29/66 ,  H01L21/67 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/67069 ,  H01L21/67075 ,  H01L29/66431 ,  H01L29/66636 ,  H01L29/778

Abstract: A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.