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11.发明授权公开(公告)号：US11874736B2
公开(公告)日：2024-01-16
申请号：US17399081
申请日：2021-08-11
Applicant: APPLE INC.
Inventor： Yonathan Tate , Nir Tishbi
CPC classification number: G06F11/1068 , G11C16/04 , G11C29/52 , H03M13/45
Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.
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公开(公告)号：US11621048B2
公开(公告)日：2023-04-04
申请号：US17388048
申请日：2021-07-29
Applicant: APPLE INC.
Inventor： Yonathan Tate , Ilia Benkovitch , Michael Jeffet , Nir Tishbi , Roy Roth , Ruby Mizrahi
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
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公开(公告)号：US20230031584A1
公开(公告)日：2023-02-02
申请号：US17388048
申请日：2021-07-29
Applicant: APPLE INC.
Inventor： Yonathan Tate , Ilia Benkovitch , Michael Jeffet , Nir Tishbi , Roy Roth , Ruby Mizrahi
Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.
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公开(公告)号：US10884855B1
公开(公告)日：2021-01-05
申请号：US16535115
申请日：2019-08-08
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Yonathan Tate , Michael Tsohar , Naftali Sommer , Eyal Gurgi
IPC: G06F11/10 , G11C29/52 , G11C29/04 , H04L1/00 , H03M13/00 , H03M13/11 , G06F9/30 , G11C11/408 , G11C11/4074 , G11C11/56 , G11C11/409
Abstract: A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np·NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.
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15.发明申请公开(公告)号：US20190035485A1
公开(公告)日：2019-01-31
申请号：US15658430
申请日：2017-07-25
Applicant: Apple Inc.
Inventor： Yonathan Tate , Tomer Ish-Shalom
CPC classification number: G11C29/42 , G06F11/1012 , G06F11/1076 , G11C29/44
Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to read from a group of the memory cells a code word encoded using an Error Correction Code (ECC), by sensing the memory cells using at least first and second read thresholds for producing respective first and second readouts, to calculate, based on at least one of the first and second readouts, (i) a syndrome weight that is indicative of an actual number of errors contained in the code word, and (ii) a mid-zone count of the memory cells for which the first readout differs from the second readout, and, to evaluate a performance measure for the memory cells, based on the calculated syndrome weight and mid-zone count.
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Patent Agency Ranking
公开(公告)号：US10128869B2
公开(公告)日：2018-11-13
申请号：US15156356
申请日：2016-05-17
Applicant: Apple Inc.
Inventor： Yonathan Tate , Moti Teitel
Abstract: A decoder includes one or more Variable-Node Processors (VNPs) that hold respective variables, and logic circuitry. The logic circuitry is configured to decode a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations such that each iteration involves processing of at least some of the variables, to hold one or more auxiliary equations derived from the check equations, so that a number of the auxiliary equations is smaller than a number of the check equations, to evaluate the auxiliary equations, during the sequence of iterations, using the variables, and, in response to detecting that the variables satisfy the auxiliary equations, to terminate the sequence of iterations and output the variables as the decoded code word.
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公开(公告)号：US20170163288A1
公开(公告)日：2017-06-08
申请号：US14961913
申请日：2015-12-08
Applicant: Apple Inc.
Inventor： Yonathan Tate , Asaf Landau , Micha Anholt
CPC classification number: H03M13/1131 , G06F11/0727 , G06F11/076 , H03M13/1128 , H03M13/1137 , H03M13/114 , H03M13/116
Abstract: A decoder includes an interface and circuitry. The interface is configured to receive a code word that was encoded using a Quasi-Cyclic Low Density Parity Check (QC-LDPC) Error Correcting Code (ECC) represented by multiple check equations that are defined over multiple variables. The circuitry is configured to decode the code word by iteratively processing multiple layers that each includes a respective subset of the variables of the code word, and producing per each layer one or more count updates, and to generate a total number of errors corrected over the entire code word by accumulating the count updates.
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18.发明申请公开(公告)号：US20170047948A1
公开(公告)日：2017-02-16
申请号：US14823061
申请日：2015-08-11
Applicant: APPLE INC.
Inventor： Moti Teitel , Tomer Ish-Shalom , Yonathan Tate
IPC: H03M13/00
CPC classification number: H03M13/616 , H03M13/116 , H03M13/611 , H03M13/6502
Abstract: A method for data encoding includes receiving a data vector to be encoded into a code word in accordance with a code defined by a parity-check matrix H. An intermediate vector s is produced by multiplying the data vector by a data sub-matrix Hs of the parity-check matrix H. A parity part of the code word is derived by applying a sequence of operations to the intermediate vector s based on a decomposition of a parity sub-matrix Hp of the matrix H using matrices A, C, U and V, in which decomposition A is a block triangular matrix that has the same size as Hp, C is matrix that is smaller than Hp, and the matrices U and V are placement matrices that are selected so that A, C, U and V satisfy a matrix equation Hp=A+UCV.
Abstract translation: 一种用于数据编码的方法包括：根据由奇偶校验矩阵H定义的代码，将要编码的数据向量接收到码字中。通过将数据矢量乘以数据子矩阵Hs 奇偶校验矩阵H.通过基于使用矩阵A，C，U的矩阵H的奇偶校验子矩阵Hp的分解，向中间向量s应用一系列操作来导出码字的奇偶校验部分， V，其中分解A是具有与Hp相同大小的块三角矩阵，C是小于Hp的矩阵，矩阵U和V是选择为使得A，C，U和V满足的放置矩阵 矩阵方程Hp = A + UCV。
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公开(公告)号：US12158806B1
公开(公告)日：2024-12-03
申请号：US18341807
申请日：2023-06-27
Applicant: APPLE INC.
Inventor： Yonathan Tate , Amit Pinchas Aylon
Abstract: A controller includes an interface and a processor. The interface communicates with memory cells. The processor reads a Code Word (CW) from the memory cells using read thresholds to produce respective readouts, the read thresholds defining zones, identifies a subgroup of the memory cells associated with zones positioned about a Read Voltage (RV) predetermined between adjacent first and second Programming Voltages (PVs), estimates for each zone, based on the readouts, first and second cumulative counts of the memory cells corresponding to the first and second PVs, models first and second PDFs associated respectively with the memory cells programmed to the first and second PVs, based on the first and second cumulative counts, calculates for the zones respective reliability measures, based on the first and second PDFs, and assigns the reliability measures to bits of the CW, and decodes the CW by applying soft decoding to the assigned reliability measures.
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公开(公告)号：US12148496B2
公开(公告)日：2024-11-19
申请号：US17852647
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Nir Tishbi , Roy Roth , Yonathan Tate
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.
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