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公开(公告)号：US12216161B2
公开(公告)日：2025-02-04
申请号：US18323946
申请日：2023-05-25
Applicant: Apple Inc.
Inventor： Bo Yang , Antonietta Oliva , Michael R. Seningen , Vasu P. Ganti , Vijay M. Bettada
IPC: G01R31/00 , G01R31/3185
Abstract: An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.
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公开(公告)号：US12072810B2
公开(公告)日：2024-08-27
申请号：US18475890
申请日：2023-09-27
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
CPC classification number: G06F12/10 , G06F12/06 , G06F17/16 , G11C5/144 , G11C5/148 , G11C7/1006 , G11C8/06 , G11C11/419
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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公开(公告)号：US12066938B2
公开(公告)日：2024-08-20
申请号：US18360352
申请日：2023-07-27
Applicant: Apple Inc.
Inventor： Michael R. Seningen
IPC: G06F12/08 , G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60
Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.
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公开(公告)号：US20240232077A9
公开(公告)日：2024-07-11
申请号：US18360352
申请日：2023-07-27
Applicant: Apple Inc.
Inventor： Michael R. Seningen
IPC: G06F12/0802
CPC classification number: G06F12/0802 , G06F2212/60
Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.
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公开(公告)号：US20220414009A1
公开(公告)日：2022-12-29
申请号：US17929544
申请日：2022-09-02
Applicant: Apple Inc.
Inventor： Michael R. Seningen
IPC: G06F12/0802
Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.
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Patent Agency Ranking
公开(公告)号：US20160240266A1
公开(公告)日：2016-08-18
申请号：US14621527
申请日：2015-02-13
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Michael A. Dreesen , Edward M. McCombs
CPC classification number: G11C29/04 , G11C5/147 , G11C7/00 , G11C11/417 , G11C29/12005 , G11C29/50 , G11C2029/5002 , G11C2029/5602
Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.
Abstract translation: 公开了对存储器进行干扰测试的方法和装置。 电路可以被配置为将测试数据存储到一个或多个数据存储单元中。 调节电路可以将耦合到一个或多个数据存储单元的电源的电平从第一电平调整到第二电平。 一旦电源的电压电平达到第二电平，电路就可以对一个或多个数据存储单元执行读取操作。 在读取操作完成时，调节电路可以将电源的电压电平恢复到第一电平，并且电路可以执行另一读取操作，其结果可以与测试数据进行比较。
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公开(公告)号：US09412469B1
公开(公告)日：2016-08-09
申请号：US14621527
申请日：2015-02-13
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Michael A. Dreesen , Edward M. McCombs
CPC classification number: G11C29/04 , G11C5/147 , G11C7/00 , G11C11/417 , G11C29/12005 , G11C29/50 , G11C2029/5002 , G11C2029/5602
Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.
Abstract translation: 公开了对存储器进行干扰测试的方法和装置。 电路可以被配置为将测试数据存储到一个或多个数据存储单元中。 调节电路可以将耦合到一个或多个数据存储单元的电源的电平从第一电平调整到第二电平。 一旦电源的电压电平达到第二电平，电路就可以对一个或多个数据存储单元执行读取操作。 在读取操作完成时，调节电路可以将电源的电压电平恢复到第一电平，并且电路可以执行另一读取操作，其结果可以与测试数据进行比较。
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公开(公告)号：US20140010030A1
公开(公告)日：2014-01-09
申请号：US14024017
申请日：2013-09-11
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Michael E. Runas
IPC: G11C7/06
CPC classification number: G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。
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19.发明申请公开(公告)号：US20130141073A1
公开(公告)日：2013-06-06
申请号：US13755403
申请日：2013-01-31
Applicant: APPLE INC.
Inventor： Michael E. Runas , Michael R. Seningen
IPC: G05F3/02
CPC classification number: G05F3/02 , H03K19/0019
Abstract: This disclosure describes a time varying power supply that may include a resonator circuit comprising an inductor having first and second terminals, a first capacitor coupled to the first terminal, and a second capacitor coupled to the second terminal, where the first capacitor produces a first time varying power supply output and wherein the second capacitor produces a second time varying power supply output. The time varying power supply may further include an exciter circuit comprising a first PFET and a first NFET coupled to the first terminal and a second PFET and a second NFET coupled to the second terminal. The first and second PFETs and the first and second NFETs may be coupled to a corresponding one of four non-overlapping clock phases.
Abstract translation: 本公开描述了时变电源，其可以包括谐振器电路，其包括具有第一和第二端子的电感器，耦合到第一端子的第一电容器和耦合到第二端子的第二电容器，其中第一电容器产生第一次 变化的电源输出，并且其中第二电容器产生第二时变电源输出。 时变电源还可以包括激励器电路，其包括耦合到第一端子的第一PFET和第一NFET以及耦合到第二端子的第二PFET和第二NFET。 第一和第二PFET以及第一和第二NFET可以耦合到四个非重叠时钟相位中的对应的一个。
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公开(公告)号：US11803480B2
公开(公告)日：2023-10-31
申请号：US17662500
申请日：2022-05-09
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
CPC classification number: G06F12/10 , G06F12/06 , G06F17/16 , G11C5/144 , G11C5/148 , G11C7/1006 , G11C8/06 , G11C11/419
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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