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241 条记录 (耗时 0.026 秒)

    Current cancellation for non-volatile memory
    11.
    发明授权
    Current cancellation for non-volatile memory 有权
    当前取消非易失性存储器

    公开(公告)号：US07965565B2

    公开(公告)日：2011-06-21

    申请号：US12502208

    申请日：2009-07-13

    申请人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    发明人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    IPC分类号： G11C7/00

    CPC分类号： G11C11/1673

    摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.

    摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。 提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。 此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

    Current cancellation for non-volatile memory
    13.
    发明授权
    Current cancellation for non-volatile memory 有权
    当前取消非易失性存储器

    公开(公告)号：US08203894B2

    公开(公告)日：2012-06-19

    申请号：US13081170

    申请日：2011-04-06

    申请人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    发明人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    IPC分类号： G11C7/22

    CPC分类号： G11C11/1673

    摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.

    摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。 提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。 此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

    Bit set modes for a resistive sense memory cell array
    15.
    发明授权
    Bit set modes for a resistive sense memory cell array 有权
    电阻读出存储单元阵列的位设置模式

    公开(公告)号：US08934281B2

    公开(公告)日：2015-01-13

    申请号：US13274876

    申请日：2011-10-17

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

    摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

    Computer memory device with multiple interfaces
    16.
    发明授权
    Computer memory device with multiple interfaces 有权
    具有多个接口的计算机存储设备

    公开(公告)号：US08194437B2

    公开(公告)日：2012-06-05

    申请号：US12352713

    申请日：2009-01-13

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/44

    CPC分类号： G11C11/22

    摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

    摘要翻译： 各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。 在一些实施例中，主机接合第一接口。 具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。 通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

    Bit set modes for a resistive sense memory cell array
    17.
    发明授权
    Bit set modes for a resistive sense memory cell array 有权
    电阻读出存储单元阵列的位设置模式

    公开(公告)号：US08040713B2

    公开(公告)日：2011-10-18

    申请号：US12352693

    申请日：2009-01-13

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

    摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

    Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array
    18.
    发明授权
    Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array 有权
    同时将多个可寻址的用户数据块写入电阻读出存储单元阵列

    公开(公告)号：US07944729B2

    公开(公告)日：2011-05-17

    申请号：US12360931

    申请日：2009-01-28

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00

    CPC分类号： G11C8/06 ,  G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/1208

    摘要： Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.

    摘要翻译： 公开了用于将数据存储到半导体存储器阵列的非易失性电阻读出存储器（RSM）存储器单元的方法和装置，包括但不限于电阻随机存取存储器（RRAM）和自旋转矩传递随机存取存储器（STTRAM或STRAM ） 细胞。 根据各种实施例，来自主机设备的多个可寻址数据块被存储在缓冲器中。 每个可寻址数据块的至少一部分被串行地传送到多个寄存器的单独寄存器。 然后，所述可寻址数据块的传送部分从寄存器同时传送到阵列的所选RSM单元。