公开(公告)号：US20210057642A1

公开(公告)日：2021-02-25

申请号：US17089798

申请日：2020-11-05

Applicant: Allegro MicroSystems, LLC

Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Bryan Cadugan ,  Sundar Chetlur ,  Harianto Wong

IPC: H01L43/12

Abstract: An apparatus including a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.

公开(公告)号：US10468485B2

公开(公告)日：2019-11-05

申请号：US15606043

申请日：2017-05-26

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Washington Lamar

IPC: H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

公开(公告)号：US20190285667A1

公开(公告)日：2019-09-19

申请号：US16421982

申请日：2019-05-24

Applicant: Allegro MicroSystems, LLC

Inventor： Shaun D. Milano ,  Bryan Cadugan ,  Michael C. Doogue ,  Alexander Latham ,  William P. Taylor ,  Harianto Wong ,  Sundar Chetlur

IPC: G01R15/14 ,  G01R15/20 ,  G01R19/00

Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.

公开(公告)号：US20190067562A1

公开(公告)日：2019-02-28

申请号：US15689185

申请日：2017-08-29

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Harianto Wong ,  Maxim Klebanov ,  William P. Taylor ,  Michael C. Doogue

IPC: H01L43/06 ,  H01L43/04 ,  H01L43/08 ,  H01L43/14 ,  H01L25/065

Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.

公开(公告)号：US20240120371A1

公开(公告)日：2024-04-11

申请号：US18045528

申请日：2022-10-11

Applicant: Allegro MicroSystems, LLC

Inventor： James McClay ,  Maxim Klebanov ,  Sundar Chetlur ,  Thomas S. Chung

IPC: H01L29/06 ,  H01L27/11524 ,  H01L29/788

CPC classification number: H01L29/0646 ,  H01L27/11524 ,  H01L29/7883

Abstract: Methods and apparatus for a device that includes a circuit, such as a memory cell, and an isolation structure to electrically isolate the circuit cell. The isolation structure can include a p-type substrate, a first series of p-type material extending to the p-type substrate, and a second series of p-type material extending to the p-type substrate. The first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material. In some embodiments, the first series of p-type material comprises p-type well regions. In some embodiments, the first series of p-type material comprises deep trench isolation.

公开(公告)号：US20230413687A1

公开(公告)日：2023-12-21

申请号：US17807196

申请日：2022-06-16

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  G01R33/07

CPC classification number: H01L43/04 ,  H01L43/065 ,  H01L43/10 ,  G01R33/077

Abstract: In one aspect, a Hall effect device includes an implantation layer; an epitaxial layer located above the implantation layer; a trench filled with a dielectric material and extending from a top surface of the epitaxial layer into the implantation layer and defining an enclosed region; a buried layer the epitaxial layer from the implantation layer within the enclosed region; and a contact pad located on the epitaxial layer. The trench reduces a current from the contact pad from traveling in a lateral direction orthogonal to a vertical direction and enables the current to travel in the vertical direction.

公开(公告)号：US20230299195A1

公开(公告)日：2023-09-21

申请号：US17695029

申请日：2022-03-15

Applicant: Allegro MicroSystems, LLC

Inventor： Thomas S. Chung ,  Chung C. Kuo ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0852

Abstract: In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.

公开(公告)号：US11598830B1

公开(公告)日：2023-03-07

申请号：US17653484

申请日：2022-03-04

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Yen Ting Liu ,  Paolo Campiglio

IPC: G01R33/09

Abstract: Methods and apparatus for a sensor including a series of tunneling magnetoresistance (TMR) pillars and a heatsink adjacent to at least one of the TMR pillars, where the heatsink comprises Titanium Nitride (TiN).

公开(公告)号：US11303116B2

公开(公告)日：2022-04-12

申请号：US16115901

申请日：2018-08-29

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H02H9/04 ,  H02H1/00

Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

公开(公告)号：US11262385B2

公开(公告)日：2022-03-01

申请号：US16421982

申请日：2019-05-24

Applicant: Allegro MicroSystems, LLC

Inventor： Shaun D. Milano ,  Bryan Cadugan ,  Michael C. Doogue ,  Alexander Latham ,  William P. Taylor ,  Harianto Wong ,  Sundar Chetlur

IPC: G01R15/14 ,  G01R15/20 ,  G01R19/00

Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.