Invention Grant
- Patent Title: Metal-oxide semiconductor (MOS) device structure based on a poly-filled trench isolation region
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Application No.: US15606043Application Date: 2017-05-26
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Publication No.: US10468485B2Publication Date: 2019-11-05
- Inventor: Sundar Chetlur , Maxim Klebanov , Washington Lamar
- Applicant: Allegro MicroSystems, LLC
- Applicant Address: US NH Manchester
- Assignee: Allegro MicroSystems, LLC
- Current Assignee: Allegro MicroSystems, LLC
- Current Assignee Address: US NH Manchester
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L27/088 ; H01L27/02 ; H01L21/8234 ; H01L29/423 ; H01L29/78 ; H01L29/51 ; H01L29/06

Abstract:
A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.
Public/Granted literature
- US20180342500A1 METAL-OXIDE SEMICONDUCTOR (MOS) DEVICE STRUCTURE BASED ON A POLY-FILLED TRENCH ISOLATION REGION Public/Granted day:2018-11-29
Information query
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