公开(公告)号：US20210175070A1

公开(公告)日：2021-06-10

申请号：US17045323

申请日：2019-04-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Rui CHENG ,  Yi YANG ,  Karthik JANAKIRAMAN

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/324

Abstract: Methods of conformally doping three dimensional structures are discussed. Some embodiments utilize conformal silicon films deposited on the structures. The silicon films are doped after deposition to comprise halogen atoms. The structures are then annealed to dope the structures with halogen atoms from the doped silicon films.

公开(公告)号：US20200335338A1

公开(公告)日：2020-10-22

申请号：US16821759

申请日：2020-03-17

Applicant: Applied Materials, Inc.

Inventor： Tzu-Shun YANG ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Zubin HUANG ,  Diwakar KADLAYA ,  Meenakshi GUPTA ,  Srinivas GUGGILLA ,  Yung-chen LIN ,  Hidetaka OSHIO ,  Chao LI ,  Gene LEE

IPC: H01L21/033

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

公开(公告)号：US20200051815A1

公开(公告)日：2020-02-13

申请号：US16659194

申请日：2019-10-21

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Shishi JIANG ,  Rui CHENG ,  Abhijit Basu MALLICK

IPC: H01L21/02

Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.

公开(公告)号：US20190019724A1

公开(公告)日：2019-01-17

申请号：US15991376

申请日：2018-05-29

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Yi YANG ,  Abhijit Basu MALLICK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3215

Abstract: Methods for seam and void-free gapfilling, such as gapfilling high aspect ratio trenches with amorphous silicon, are provided. A method generally includes depositing amorphous silicon over a semiconductor device having one or more features thereon, annealing the deposited amorphous silicon to heal one or more seams in the deposited amorphous silicon between the one or more features, and etching the annealed amorphous silicon to remove one or more voids in the annealed amorphous silicon between the one or more features. The deposition, anneal, and etch processes are generally repeated any suitable number of times to achieve amorphous silicon gapfill without any seam or void between the one or more features.

公开(公告)号：US20160027614A1

公开(公告)日：2016-01-28

申请号：US14697385

申请日：2015-04-27

Applicant: Applied Materials, Inc.

Inventor： Pramit MANNA ,  Abhijit Basu MALLICK ,  Mukund SRINIVASAN ,  Rui CHENG

IPC: H01J37/32 ,  C23C16/06 ,  C23C16/26 ,  C23C16/04

CPC classification number: C23C16/26 ,  C23C16/042 ,  C23C16/06 ,  C23C16/30 ,  H01J37/32091

Abstract: Embodiments of the present disclosure relate to a metal-doped amorphous carbon hardmask for etching the underlying layer, layer stack, or structure. In one embodiment, a method of processing a substrate in a processing chamber includes exposing a substrate to a gas mixture comprising a carbon-containing precursor and a metal-containing precursor, reacting the carbon-containing precursor and the metal-containing precursor in the processing chamber to form a metal-doped carbon layer over a surface of the substrate, forming in the metal-doped carbon layer a defined pattern of through openings, and transferring the defined pattern to an underlying layer beneath the metal-doped carbon layer using the metal-doped carbon layer as a mask. An etch hardmask using the inventive metal-doped amorphous carbon film provides reduced compressive stress, high hardness, and therefore higher etch selectivity.

Abstract translation: 本公开的实施例涉及用于蚀刻下层，层叠或结构的金属掺杂非晶碳硬掩模。 在一个实施方案中，在处理室中处理衬底的方法包括将衬底暴露于包含含碳前体和含金属的前体的气体混合物中，使该含碳前体和含金属的前体在加工过程中反应 室，以在衬底的表面上形成金属掺杂碳层，在金属掺杂碳层中形成限定图形的通孔，并将定义的图案转移到金属掺杂碳层下方的下层，使用金属 掺杂碳层作为掩模。 使用本发明的金属掺杂的非晶碳膜的蚀刻硬掩模提供降低的压缩应力，高硬度，因此提高了蚀刻选择性。

公开(公告)号：US20230178419A1

公开(公告)日：2023-06-08

申请号：US18103850

申请日：2023-01-31

Applicant: Applied Materials, Inc.

Inventor： Benjamin COLOMBEAU ,  Theresa Kramer GUARINI ,  Malcolm BEVAN ,  Rui CHENG

IPC: H01L21/762 ,  H01L21/02 ,  H01J37/32 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50

CPC classification number: H01L21/76227 ,  H01L21/02247 ,  H01L21/02252 ,  H01J37/32743 ,  H01J37/32788 ,  C23C16/56 ,  C23C16/24 ,  C23C16/28 ,  C23C16/50 ,  H01J37/32816 ,  H01J2237/332

Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.

公开(公告)号：US20220406594A1

公开(公告)日：2022-12-22

申请号：US17352039

申请日：2021-06-18

Applicant: Applied Materials, Inc.

Inventor： Aykut AYDIN ,  Rui CHENG ,  Karthik JANAKIRAMAN ,  Abhijit B. MALLICK ,  Takehito KOSHIZAWA ,  Bo QI

IPC: H01L21/02

Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.

公开(公告)号：US20200373159A1

公开(公告)日：2020-11-26

申请号：US16853500

申请日：2020-04-20

Applicant: Applied Materials, Inc.

Inventor： Takehito KOSHIZAWA ,  Rui CHENG ,  Tejinder SINGH ,  Hidetaka OSHIO

IPC: H01L21/033 ,  H01L21/311

Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.

公开(公告)号：US20200321210A1

公开(公告)日：2020-10-08

申请号：US16797111

申请日：2020-02-21

Applicant: Applied Materials, Inc.

Inventor： Meenakshi GUPTA ,  Rui CHENG ,  Srinivas GUGGILLA ,  Karthik JANAKIRAMAN ,  Diwakar N. KEDLAYA ,  Zubin HUANG

IPC: H01L21/027 ,  H01L21/32 ,  H01L21/02

Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.

公开(公告)号：US20180277370A1

公开(公告)日：2018-09-27

申请号：US15988830

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan KWON ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Er-Xuan PING ,  Jaesoo AHN

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/308 ,  H01L21/02 ,  H01L49/02 ,  H01L21/311 ,  H01L27/11582

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.