公开(公告)号：US20150249833A1

公开(公告)日：2015-09-03

申请号：US14503200

申请日：2014-09-30

Applicant: Apple Inc.

Inventor： Alexandros Tourapis ,  David Singer ,  Guy Cote ,  Timothy J. Millet

IPC: H04N19/154 ,  H04N19/124 ,  H04N19/40 ,  H04N19/176 ,  H04N19/103 ,  H04N19/196

CPC classification number: H04N19/154 ,  H04N19/103 ,  H04N19/124 ,  H04N19/176 ,  H04N19/196 ,  H04N19/40

Abstract: Embodiments of the present invention may provide a video coder. The video coder may include an encoder to perform coding operations on a video signal in a first format to generate coded video data, and a decoder to decode the coded video data. The video coder may also include an inverse format converter to convert the decoded video data to second format that is different than the first format and an estimator to generate a distortion metric using the decoded video data in the second format and the video signal in the second format. The encoder may adjust the coding operations based on the distortion metric.

Abstract translation: 本发明的实施例可以提供视频编码器。 视频编码器可以包括编码器，以对第一格式的视频信号执行编码操作，以产生编码的视频数据，以及解码器，对编码的视频数据进行解码。 视频编码器还可以包括逆格式转换器，用于将解码的视频数据转换为与第一格式不同的第二格式，以及估计器，以使用第二格式的解码视频数据和第二格式的视频信号来生成失真度量 格式。 编码器可以基于失真度量来调整编码操作。

公开(公告)号：US20150160701A1

公开(公告)日：2015-06-11

申请号：US14097491

申请日：2013-12-05

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: G06F1/18

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US10573319B2

公开(公告)日：2020-02-25

申请号：US16546574

申请日：2019-08-21

Applicant: Apple Inc. ,  Diane Culbert

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/22 ,  G10L15/28 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/32 ,  G06F3/16 ,  G10L25/48 ,  G10L15/08

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US20190287532A1

公开(公告)日：2019-09-19

申请号：US16397057

申请日：2019-04-29

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/28 ,  G06F1/3287 ,  G06F1/3228 ,  G06F3/16 ,  G10L15/22 ,  G06F1/32

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US10313683B2

公开(公告)日：2019-06-04

申请号：US14474114

申请日：2014-08-30

Applicant: Apple Inc.

Inventor： Joseph J. Cheng ,  Timothy J. Millet ,  Shun Wai Go ,  Guy Cote

IPC: H04N19/172 ,  H04N19/176 ,  H04N19/46 ,  G06F9/46 ,  G06F9/48 ,  H04N19/129 ,  H04N19/127 ,  H04N19/174 ,  H04N19/42 ,  H04N19/40 ,  H04N19/182

Abstract: A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

公开(公告)号：US20160218094A1

公开(公告)日：2016-07-28

申请号：US15087200

申请日：2016-03-31

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US20160170677A1

公开(公告)日：2016-06-16

申请号：US15006286

申请日：2016-01-26

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

公开(公告)号：US09262798B2

公开(公告)日：2016-02-16

申请号：US14263424

申请日：2014-04-28

Applicant: Apple Inc.

Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet

IPC: G09G5/39 ,  G06T1/60 ,  G09G5/36 ,  G09G5/14

CPC classification number: G06T1/60 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/10 ,  G09G2360/12 ,  G09G2360/127

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索和处理顶部帧分组，以根据顶部帧分组的内容更新一个或多个参数寄存器。 控制电路可以发出DMA请求，用从系统存储器传送的帧分组填充参数缓冲器，其中帧分组可以由在中央处理单元上执行的应用（或软件）写入。

公开(公告)号：US20150347287A1

公开(公告)日：2015-12-03

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. De Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：US09087393B2

公开(公告)日：2015-07-21

申请号：US13788209

申请日：2013-03-07

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Timothy J. Millet

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G06T1/60 ,  G09G5/006 ,  G09G2340/0442 ,  G09G2340/0492 ,  G09G2360/125 ,  G09G2370/10

Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。