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    Cache implementing multiple replacement policies
    4.
    发明授权
    Cache implementing multiple replacement policies 有权
    缓存实现多个替换策略

    公开(公告)号：US08719509B2

    公开(公告)日：2014-05-06

    申请号：US13755999

    申请日：2013-01-31

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F13/00

    CPC classification number: G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

    Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

    Abstract translation: 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

    Cache Implementing Multiple Replacement Policies
    5.
    发明申请
    Cache Implementing Multiple Replacement Policies 有权
    缓存实现多个替换策略

    公开(公告)号：US20130151781A1

    公开(公告)日：2013-06-13

    申请号：US13755999

    申请日：2013-01-31

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/12 ,  G06F12/08

    CPC classification number: G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

    Abstract: In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

    Abstract translation: 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。

    Combined transparent/non-transparent cache
    6.
    发明授权
    Combined transparent/non-transparent cache 有权

    公开(公告)号：US10241705B2

    公开(公告)日：2019-03-26

    申请号：US15352693

    申请日：2016-11-16

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/123 ,  G06F12/0831 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/0846 ,  G06F12/0853

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Combined Transparent/Non-Transparent Cache
    8.
    发明申请
    Combined Transparent/Non-Transparent Cache 审中-公开
    组合透明/不透明缓存

    公开(公告)号：US20150149734A1

    公开(公告)日：2015-05-28

    申请号：US14611423

    申请日：2015-02-02

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F12/08

    CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

    Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

    Combined transparent/non-transparent cache
    9.
    发明授权
    Combined transparent/non-transparent cache 有权

    公开(公告)号：US10776022B2

    公开(公告)日：2020-09-15

    申请号：US16266320

    申请日：2019-02-04

    Applicant: Apple Inc.

    Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

    IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/123 ,  G06F12/0831 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/0846 ,  G06F12/0853

    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

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