公开(公告)号：US06985027B2

公开(公告)日：2006-01-10

申请号：US10684438

申请日：2003-10-15

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G05F1/10

CPC分类号： G05F1/565 ,  H03F1/305

摘要： A semiconductor integrated circuit comprises a power supply voltage step down circuit and a MOS circuit group. The power supply voltage step down circuit is supplied with a power supply voltage and controlled by a standby control signal indicating an operating state or a standby state. The power supply voltage step down circuit outputs a first internal power supply voltage lower than the power supply voltage to an internal power supply line when the standby control signal indicates the operating state, and outputs a second internal power supply voltage lower than the first internal power supply voltage to the internal power supply line when the standby control signal indicates the standby state. The MOS circuit group including one or more MOS transistors which are supplied with the first or second internal power supply voltage from the internal power supply line to operate.

摘要翻译： 半导体集成电路包括电源电压降压电路和MOS电路组。 电源电压降压电路被供给电源电压并由指示操作状态或待机状态的待机控制信号控制。 当待机控制信号指示运行状态时，电源电压降压电路将低于电源电压的第一内部电源电压输出到内部电源线，并且输出低于第一内部电力的第二内部电源电压 当待机控制信号指示待机状态时，向内部电源线供电。 MOS电路组包括一个或多个MOS晶体管，其被提供有来自内部电源线的第一或第二内部电源电压以进行操作。

公开(公告)号：US06847542B2

公开(公告)日：2005-01-25

申请号：US10449536

申请日：2003-06-02

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C11/412

摘要： An SRAM cell comprising a first inverter comprising a first load element and a first driver NMOSFET, a second inverter comprising a second load element and a second driver NMOSFET and having input and output terminals cross-coupled to output and input terminals of the first inverter, respectively, a first transfer gate NMOSFET having a current path inserted between the first inverter and a first bit line and a gate connected to a word line, and a second transfer gate NMOSFET having a current path inserted between the second inverter and a second bit line and a gate connected to the word line, wherein a current drivability of the first inverter and the first transfer gate NMOSFET for the first bit line is set to be larger than that of the second inverter and the second transfer gate NMOSFET for the second bit line.

摘要翻译： 一种包括第一反相器的SRAM单元，包括第一负载元件和第一驱动器NMOSFET，第二反相器包括第二负载元件和第二驱动器NMOSFET，并具有与第一反相器的输出和输入端交叉耦合的输入和输出端子， 分别具有插入在第一反相器和第一位线之间的电流通路和连接到字线的栅极的第一传输门NMOSFET，以及具有插入在第二反相器和第二位线之间的电流通路的第二传输门NMOSFET 以及连接到字线的栅极，其中用于第一位线的第一反相器和第一传输门NMOSFET的电流驱动能力被设置为大于第二位线的第二反相器和第二传输门NMOSFET的电流驱动能力 。

公开(公告)号：US5995430A

公开(公告)日：1999-11-30

申请号：US25860

申请日：1998-02-19

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/1006 ,  G11C2207/104

摘要： An overlaid DQ type DRAM of a clock synchronous type is provided with a column address transition detector circuit, to control pre-charging and equalizing of pairs of DQ lines. An address for selecting a DQ line muptiplexer in a stage prior to a DQ buffer is set to a predetermined column address, and a transition of a column address is detected in a first pipeline stage of a column access path. When only the bit of the predetermined column address changes with the other column address bits kept unchanged, DQ lines are pre-charged and equalized.

摘要翻译： 具有时钟同步型的叠加的DQ型DRAM具有列地址转换检测器电路，以控制DQ线对的预充电和均衡。 将用于在DQ缓冲器之前的阶段中选择DQ线多路复用器的地址设置为预定列地址，并且在列访问路径的第一流水线级中检测列地址的转换。 当只有预定列地址的位改变而其他列地址位保持不变时，DQ线被预充电和均衡。

公开(公告)号：US5890186A

公开(公告)日：1999-03-30

申请号：US895863

申请日：1997-07-17

申请人： Katsuhiko Sato ,  Shinji Miyano ,  Tomoaki Yabe ,  Tohru Furuyama

发明人： Katsuhiko Sato ,  Shinji Miyano ,  Tomoaki Yabe ,  Tohru Furuyama

IPC分类号： G11C11/409 ,  G06F12/08 ,  G11C7/10 ,  G11C11/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/34

CPC分类号： G11C7/1051 ,  G11C11/005

摘要： When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an "H" level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an "H" level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.

摘要翻译： 当存储在存储单元阵列的存储单元中的数据被写入高速缓冲存储器时，写入信号LW被设置为“H”电平。 写入信号LW通过初始化控制电路输入到数据线对初始化选择电路，信号EQE在所有列中被设置为“H”电平。 然后，数据线对初始化电路将所有列中的数据线对的电位设置在相同的电平。 当写信号LW通过传输门控制电路输入到传输门时，所有列中的传输门被接通。 传输门控制电路的延迟时间与初始化控制的延迟时间相同或更大。

公开(公告)号：US5640351A

公开(公告)日：1997-06-17

申请号：US601859

申请日：1996-02-15

申请人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

发明人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C7/10

摘要： According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.

摘要翻译： 根据本发明，通过选择列来形成多个存储单元阵列共用的数据总线，以防止发生数据冲突。 具体地说，两个存储单元阵列共有数据总线。 列解码器被提供有控制信号以控制列选择逻辑电路。 列选择逻辑电路被如此控制，以便在同时访问两个单元阵列期间防止响应于控制信号读出到数据总线的数据彼此相冲突。

公开(公告)号：US5299164A

公开(公告)日：1994-03-29

申请号：US21515

申请日：1993-02-23

申请人： Hideki Takeuchi ,  Shigeyuki Hayakawa ,  Tomoaki Yabe

发明人： Hideki Takeuchi ,  Shigeyuki Hayakawa ,  Tomoaki Yabe

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/84

摘要： An internal row address signal output from an address buffer is supplied to first and second row partial decoders. A programming circuit is programmed to store information indicating whether the redundant function is used or not and a defective address corresponding to a defective main word line or defective memory cell in a main memory cell array. The defective row address and the internal row adders signal are compared with each other by the programming circuit and the spare decoder, a control signal corresponding to the coincidence/non-coincidence of the compared row addresses is output, and a partial decode signal of the internal row address signal is output when the compared row addresses coincide with each other. The second partial decoder receives a control signal output from the spare decoder and outputs a partial decode signal of the internal row address signal when the control signal indicates the non-coincidence of the compared row addresses. The partial decode signals output from the first and second row partial decoders are supplied to the main row decoder which in turn selects one of main word lines in the main memory cell array. The partial decode signal output from the spare decoder is supplied to a spare row decoder which in turn selects one of spare word lines in a spare memory cell array.

摘要翻译： 从地址缓冲器输出的内部行地址信号被提供给第一和第二行部分解码器。 编程电路被编程为存储指示是否使用冗余功能的信息以及与主存储单元阵列中的有缺陷的主字线或有缺陷的存储单元相对应的缺陷地址。 通过编程电路和备用解码器将有缺陷的行地址和内部行加法器信号相互比较，输出与比较的行地址的一致/非重合相对应的控制信号，并且输出 当比较的行地址彼此一致时，输出内部行地址信号。 当控制信号指示比较的行地址的不一致时，第二部分解码器接收从备用解码器输出的控制信号并输出​​内部行地址信号的部分解码信号。 从第一和第二行部分解码器输出的部分解码信号被提供给主行解码器，主行解码器依次选择主存储单元阵列中的一个主字线。 从备用解码器输出的部分解码信号被提供给备用行解码器，备用行解码器又选择备用存储单元阵列中的一个备用字线。

公开(公告)号：US07791971B2

公开(公告)日：2010-09-07

申请号：US12430253

申请日：2009-04-27

申请人： Akihito Tohata ,  Tomoaki Yabe

发明人： Akihito Tohata ,  Tomoaki Yabe

IPC分类号： G11C7/00

CPC分类号： G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

摘要翻译： 一种半导体存储器件包括第一和第二单元阵列，其具有排列在行和列方向上的存储单元，连接到沿列方向排列的存储单元的第一和第二位线以及连接到列方向的第一和第二读出放大器 第一位，第二位线。 该装置还包括第一和第二虚拟单元阵列，其具有排列在行和列方向上的虚设单元，连接到沿行方向排列的虚拟单元的虚拟字线，连接到行方向的第一和第二虚拟位线 虚拟单元，沿列方向排列并接收来自虚拟字线的输出，以及第一和第二读出放大器激活电路，其根据从第一和第二虚拟位线输出的第一和第二控制信号激活第一，第二读出放大器 ， 分别。

公开(公告)号：US20100014375A1

公开(公告)日：2010-01-21

申请号：US12568253

申请日：2009-09-28

申请人： Tomoaki YABE ,  Akihito Tohata

发明人： Tomoaki YABE ,  Akihito Tohata

IPC分类号： G11C5/14 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C11/413

摘要： A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

摘要翻译： 半导体存储器件通过使用固定功率和可变功率来工作。 该装置包括多个字线，其选择存储单元阵列的行，多个字线驱动器，每个字线连接到对应的一个字线，并且包括第一CMOS栅极，第一截止开关，其被连接 在固定电源端子和第一CMOS栅极的电源端子之间并在睡眠模式下切断固定功率的开关电路，连接到多个字线并将多个字线连接到接地端子的开关电路 睡眠模式和通过使用固定功率产生可变功率并在睡眠模式下将可变功率设置为0V的功率控制电路。

公开(公告)号：US07525828B2

公开(公告)日：2009-04-28

申请号：US12052020

申请日：2008-03-20

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/046 ,  G11C29/846

摘要： A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

摘要翻译： 一种半导体存储器件，包括：第一存储器，其中输入第一地址和第一输入数据，并且将第一输出数据输入到第一地址作为搜索地址输入的内容寻址存储器，并且执行搜索 确定第一地址和缺陷地址是否彼此一致，并且当第一地址和有缺陷地址彼此一致时，输出第二地址和控制信号，第二存​​储器，当第二地址被输入时 输出对应于第二地址的冗余数据，以及多路复用器，当输入控制信号时，将输出数据从第一输出数据切换到冗余数据，并将冗余数据输出到输入/输出端。

公开(公告)号：US20080137393A1

公开(公告)日：2008-06-12

申请号：US11952441

申请日：2007-12-07

申请人： Gou FUKANO ,  Tomoaki YABE ,  Nobuaki OTSUKA

发明人： Gou FUKANO ,  Tomoaki YABE ,  Nobuaki OTSUKA

IPC分类号： G11C5/06 ,  G11C5/02

CPC分类号： G11C7/18

摘要： This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

摘要翻译： 该半导体存储器件包括具有以矩阵形式布置的多个存储单元的多个子阵列。 每个本地位线连接到在子阵列中沿列方向布置的多个存储单元。 另外，全局位线连接到多个局部位线。 列解码器连接到全局位线。 全局位线从列解码器向多个子阵列延伸，并且在与该列解码器最远的区域中形成的最远子阵列之前被切割。