An overlaid DQ type DRAM of a clock synchronous type is provided with a column address transition detector circuit, to control pre-charging and equalizing of pairs of DQ lines. An address for selecting a DQ line muptiplexer in a stage prior to a DQ buffer is set to a predetermined column address, and a transition of a column address is detected in a first pipeline stage of a column access path. When only the bit of the predetermined column address changes with the other column address bits kept unchanged, DQ lines are pre-charged and equalized.