公开(公告)号：US20050067709A1

公开(公告)日：2005-03-31

申请号：US10675260

申请日：2003-09-30

Applicant: Mark Bachman ,  Daniel Chesire ,  Sailesh Merchant ,  John Osenbach ,  Kurt Steiner

Inventor： Mark Bachman ,  Daniel Chesire ,  Sailesh Merchant ,  John Osenbach ,  Kurt Steiner

IPC: H01L21/60 ,  H01L23/00 ,  H01L23/485 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/768 ,  H01L23/562 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/05552

Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.

Abstract translation: 本文公开了一种用于加强集成电路的接触焊盘的增强系统和方法。 具体示出的是包括插入在顶部接触垫层和下面的金属层之间的加强结构的系统和方法。

公开(公告)号：US06498364B1

公开(公告)日：2002-12-24

申请号：US09489092

申请日：2000-01-21

Applicant: Stephen Downey ,  Edward Harris ,  Sailesh Merchant

Inventor： Stephen Downey ,  Edward Harris ,  Sailesh Merchant

IPC: H01L31113

CPC classification number: H01L23/5223 ,  H01L27/0688 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a capacitor for use in a semiconductor device having a damascene interconnect structure, such as a dual damascene interconnect, formed over a substrate of a semiconductor wafer. In one particularly advantageous embodiment, the capacitor, comprises a first capacitor electrode, such as copper, comprised of a portion of the damascene interconnect structure, an insulator layer formed on the damascene interconnect structure wherein the insulator layer is a passivation layer, such as silicon nitride. The passivation layer may be an outermost or final passivation layer, or it may be an interlevel passivation layer. The capacitor further includes a second capacitor electrode comprised of a conductive layer, such as aluminum, that is formed on at least a portion of the insulator layer.

Abstract translation: 本发明提供一种用于半导体器件的电容器，其具有形成在半导体晶片的衬底上的诸如双镶嵌互连的镶嵌互连结构。 在一个特别有利的实施例中，电容器包括由镶嵌互连结构的一部分组成的第一电容器电极（例如铜），形成在镶嵌互连结构上的绝缘体层，其中绝缘体层是钝化层，例如硅 氮化物。 钝化层可以是最外面的或最终的钝化层，或者它可以是层间钝化层。 电容器还包括形成在绝缘体层的至少一部分上的由诸如铝的导电层组成的第二电容器电极。

公开(公告)号：US20080026508A1

公开(公告)日：2008-01-31

申请号：US11868624

申请日：2007-10-08

Applicant: Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

Inventor： Vance Archer ,  Kouros Azimi ,  Daniel Chesire ,  Warren Gladden ,  Seung Kang ,  Taeho Kook ,  Sailesh Merchant ,  Vivian Ryan

IPC: H01L21/00

CPC classification number: H01L23/36 ,  H01L21/4871 ,  H01L25/165 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Abstract translation: 一种集成电路装置，其包括冶金结合以增强对散热器的热传导。 在半导体器件中，集成电路管芯的表面冶金地结合到散热器的表面。 在制造器件的示例性方法中，封装衬底的上表面包括内部区域和周边区域。 集成电路管芯位于衬底表面上，并且集成电路管芯的第一表面被放置成与封装衬底接触。 金属层形成在集成电路管芯的第二相对表面上。 预成型件定位在金属层上，并且散热器位于预制件上。 用预成型件形成接合层，将散热器冶金结合到集成电路管芯的第二表面。

公开(公告)号：US20070228572A1

公开(公告)日：2007-10-04

申请号：US11649015

申请日：2007-01-03

Applicant: Sailesh Chittipeddi ,  Sailesh Merchant

Inventor： Sailesh Chittipeddi ,  Sailesh Merchant

IPC: H01L23/48

CPC classification number: H01L23/53295 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.

Abstract translation: 集成电路结构包括具有形成在电介质材料层中的双镶嵌沟槽结构的金属化层。 电介质材料具有第一平面度的上表面。 金属化层包括形成在沟槽结构中的导电层，其上表面具有与电介质材料上表面相同的平面度水平。 在某些实施例中，导电层的上表面与电介质材料上表面基本共面。

公开(公告)号：US20070168818A1

公开(公告)日：2007-07-19

申请号：US11673714

申请日：2007-02-12

Applicant: Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant ,  Lisa Mullin

Inventor： Seung Kang ,  Subramanian Karthikeyan ,  Sailesh Merchant ,  Lisa Mullin

IPC: G01R31/30 ,  G06F11/00

CPC classification number: G01R31/2877 ,  G01R31/2856

Abstract: A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

Abstract translation: 半导体测试装置包括具有用于施加电信号和测量测试电路的电参数的触点的测试电路。 半导体测试装置还包括整体形成的加热电路，其包括邻近测试电路定位的至少一个电路弯道，用于升高测试电路的一部分内的温度。

公开(公告)号：US20060226535A1

公开(公告)日：2006-10-12

申请号：US11448560

申请日：2006-06-07

Applicant: Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

Inventor： Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

IPC: H01L23/04

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

公开(公告)号：US20060192647A1

公开(公告)日：2006-08-31

申请号：US11414902

申请日：2006-05-01

Applicant: Edward Harris ,  Sailesh Merchant ,  Kurt Steiner ,  Susan Vitkavage

Inventor： Edward Harris ,  Sailesh Merchant ,  Kurt Steiner ,  Susan Vitkavage

IPC: H01F5/00

CPC classification number: H01L24/10 ,  H01F41/041 ,  H01L23/5227 ,  H01L24/13 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10T29/4902 ,  H01L2924/00 ,  H01L2224/48

Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

公开(公告)号：US20100188987A1

公开(公告)日：2010-07-29

申请号：US12322028

申请日：2009-01-28

Applicant: Kouros Azimi ,  Roger Fratti ,  Sailesh Merchant ,  Mohammad Mobin ,  Kenneth Paist

Inventor： Kouros Azimi ,  Roger Fratti ,  Sailesh Merchant ,  Mohammad Mobin ,  Kenneth Paist

IPC: G08C15/00

CPC classification number: H04W48/04 ,  H04W12/06 ,  H04W64/00

Abstract: In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area.

Abstract translation: 在所描述的实施例中，无线家庭网络的元件采用学习的网络安全性。 接入点，路由器或其他无线基站发射和接收具有相应信号强度的信号。 通过无线电链路耦合到基站的无线设备在家庭的边界点移动通过家庭网络，并且在每个设备处测量信号强度并将其传送到基站。 基于从边界点测量的发射信号的信号强度信息和/或从边界点接收的信号的测量信号强度信息，基站确定网络安全区域。 基站拒绝尝试使用或加入家庭网络的设备的权限，这些设备的信号强度特性小于网络安全区域的边界值。

公开(公告)号：US20070069394A1

公开(公告)日：2007-03-29

申请号：US11459249

申请日：2006-07-21

Applicant: Mark Bachman ,  Donald Bitting ,  Sailesh Chittipeddi ,  Seung Kang ,  Sailesh Merchant

Inventor： Mark Bachman ,  Donald Bitting ,  Sailesh Chittipeddi ,  Seung Kang ,  Sailesh Merchant

IPC: H01L23/48

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening.

Abstract translation: 本发明在一个方面提供一种半导体器件，其包括位于半导体衬底之上的互连层。 钝化层位于互连层上并且具有形成在其中的焊料凸块支撑开口。 包括导电材料的支撑柱位于焊料凸块支撑开口内。

公开(公告)号：US20060065969A1

公开(公告)日：2006-03-30

申请号：US10955913

申请日：2004-09-30

Applicant: Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

Inventor： Joze Antol ,  Philip Seitzer ,  Daniel Chesire ,  Rafe Mengel ,  Vance Archer ,  Thomas Gans ,  Taeho Kook ,  Sailesh Merchant

IPC: H01L23/053

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe region 212 from the wire bond region 210 and forming the bond pad 211 over active circuitry has several advantages. By separating the probe region 212 from the wire bond region 210, the wire bond region 210 is not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond pad 211 over active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Abstract translation: 这里公开了用于衬垫加强的新型支撑结构以及用于半导体器件的新的接合焊盘设计。 新的焊盘设计通过提供与引线键合区域分离的探针区域来避免与探针测试相关的问题。 将探针区域212与引线接合区域210分离并通过有源电路形成接合焊盘211具有若干优点。 通过将探针区域212与引线键合区域210分离，引线键合区域210不会被探针测试所损坏，从而允许更可靠的引线键合。 此外，在包括金属互连层的有源电路上形成接合焊盘211允许集成电路更小。