知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

76 条记录 (耗时 0.021 秒)

    Method of making non-volatile semiconductor memory devices having large capacitance between floating and control gates
    11.
    发明授权
    Method of making non-volatile semiconductor memory devices having large capacitance between floating and control gates 失效
    制造在浮动栅极和控制栅极之间具有大电容的非易失性半导体存储器件的方法

    公开(公告)号：US5863822A

    公开(公告)日：1999-01-26

    申请号：US796597

    申请日：1997-02-07

    申请人： Kohji Kanamori ,  Yosiaki Hisamune

    发明人： Kohji Kanamori ,  Yosiaki Hisamune

    IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/42324 ,  H01L29/66825 ,  Y10S438/981

    摘要： Disclosed herein is a stacked gate type non-volatile semiconductor memory cell including source/drain regions having a first portion covered with a tunnel oxide film and a second portion covered with an insulator film. The memory cell further includes a gate insulating film formed on a channel region, wherein the tunnel insulating film is thinner than the gate oxide film and the insulator film is thicker than the gate insulating film. A floating gate is formed on the respective insulating films and a control gate is formed over the floating gate with an intervention of a second gate insulating film.

    摘要翻译： 本文公开了一种堆叠栅极型非易失性半导体存储单元，其包括具有覆盖有隧道氧化物膜的第一部分和覆盖有绝缘膜的第二部分的源极/漏极区域。 存储单元还包括形成在沟道区上的栅极绝缘膜，其中隧道绝缘膜比栅极氧化膜薄，并且绝缘膜比栅极绝缘膜厚。 在各个绝缘膜上形成浮栅，并且在第二栅极绝缘膜的介入上在浮栅上方形成控制栅极。

    Nonvolatile semiconductor device and method of manufacturing same
    12.
    发明授权
    Nonvolatile semiconductor device and method of manufacturing same 失效
    非易失性半导体器件及其制造方法

    公开(公告)号：US5838611A

    公开(公告)日：1998-11-17

    申请号：US911002

    申请日：1997-08-14

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115

    摘要： A semiconductor memory device with a contactless array structure has bit-lines formed in a semiconductor substrate by diffusion of an impurity. Word-lines (control gates) are formed on the substrate so as to intersect the bit-lines. Floating gates are disposed in intersecting regions between the bit- and word-lines. Regions of higher resistance extend in parallel to the bit-lines located on both sides of a floating gates and located in an offset manner relative to the floating gate. A thick dielectric film is formed between the regions of higher resistance and word-lines. In this semiconductor memory device, a source side injection method with higher efficiency can be utilized for electron injection to a floating gate (programming) and thereby a lower programming voltage, less power consumption, and higher degree of integration are achieved.

    摘要翻译： 具有非接触阵列结构的半导体存储器件通过杂质的扩散在半导体衬底中形成位线。 字线（控制栅极）形成在基板上以与位线相交。 浮动栅极位于位线和字线之间的交叉区域。 较高电阻的区域平行于位于浮动栅极两侧的位线并且相对于浮动栅极以偏移方式定位。 在较高电阻和字线的区域之间形成厚电介质膜。 在该半导体存储器件中，可以利用具有更高效率的源极侧注入方法用于向浮动栅极（编程）的电子注入，从而实现较低的编程电压，更低的功率消耗和更高的集成度。

    Memory device
    13.
    发明授权
    Memory device 有权

    公开(公告)号：US10134752B2

    公开(公告)日：2018-11-20

    申请号：US15393775

    申请日：2016-12-29

    申请人： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

    发明人： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

    IPC分类号： H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/04

    摘要： A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

    MEMORY DEVICE
    16.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20170373089A1

    公开(公告)日：2017-12-28

    申请号：US15393775

    申请日：2016-12-29

    申请人： Kwang Soo KIM ,  Shin Hwan KANG ,  Jae Hoon JANG ,  Kohji KANAMORI

    发明人： Kwang Soo KIM ,  Shin Hwan KANG ,  Jae Hoon JANG ,  Kohji KANAMORI

    IPC分类号： H01L27/11582 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  G11C16/26

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L27/11556

    摘要： A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

    Semiconductor device and its manufacturing method
    20.
    发明授权
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：US07439602B2

    公开(公告)日：2008-10-21

    申请号：US10915773

    申请日：2004-08-11

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/115

    摘要： A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

    摘要翻译： 已经公开了一种半导体器件，其包括由可以与堆叠的膜图案（7）自对准的沟槽隔离的存储器单元。 存储单元可以是具有可以比栅极氧化膜（30）薄的有源栅极膜（2）的闪存单元。 有源栅极膜（2）可以位于栅电极（3）下方的中心部分。 栅极氧化膜（30）可以位于栅电极（3）的端部下方。 以这种方式，可以增加沟槽（11）的肩部与栅电极（3）之间的距离。 因此，可以减小沟槽（11）的肩部中的电场集中，并且可以提高存储单元特性。