公开(公告)号：US07561693B2

公开(公告)日：2009-07-14

申请号：US10621244

申请日：2003-07-15

申请人： Kyoung Ho Choi ,  Kil Ho Lee ,  Moon Seob Song ,  Joon Woo Lee

发明人： Kyoung Ho Choi ,  Kil Ho Lee ,  Moon Seob Song ,  Joon Woo Lee

IPC分类号： H04L9/00

CPC分类号： H04L63/104 ,  H04L1/16 ,  H04W12/02

摘要： Provided are a method for automatically entering into a secure communication mode that can perform secured voice communication between a transmission terminal and a reception terminal without changing or pre-setting a conventional wireless mobile communication system by forming part of a voice signal as a token for attempting secured voice communication, and a computer-readable recording medium for recording a program that implements the method. The method of the present research includes the steps of: a) generating a token based on a data having the lowest frequency of generation among the voice data outputted from a vocoder of the wireless communication terminal; b) at a transmission terminal receiving a request for a secure communication from a user and transmitting the token to a reception terminal; and c) at the transmission terminal entering into a secure communication mode based on an acknowledge token transmitted from the reception terminal, and performing secure communication with the reception terminal.

摘要翻译： 提供了一种用于自动进入安全通信模式的方法，该安全通信模式可以在传输终端和接收终端之间执行安全的语音通信，而不需要通过将语音信号的一部分形成为用于尝试的令牌来改变或预设常规的无线移动通信系统 安全的语音通信，以及用于记录实现该方法的程序的计算机可读记录介质。 本研究的方法包括以下步骤：a）基于从无线通信终端的声码器输出的语音数据中具有最低生成频率的数据生成令牌; b）在发送终端接收来自用户的安全通信的请求并将该令牌发送到接收终端; 以及c）在所述传输终端基于从所述接收终端发送的确认令牌进入安全通信模式，并且执行与所述接收终端的安全通信。

公开(公告)号：US20060194451A1

公开(公告)日：2006-08-31

申请号：US11342370

申请日：2006-01-27

申请人： Kil-Ho Lee ,  Chan Lim

发明人： Kil-Ho Lee ,  Chan Lim

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  Y10S257/914 ,  H01L2924/00

摘要： A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

摘要翻译： 提供了高k电介质膜，形成高k电介质膜的方法以及形成相关半导体器件的方法。 高k电介质膜包括具有第一氮含量和第一硅含量的金属 - 氮氧化硅的底层和具有第二氮含量和第二硅含量的金属 - 氮氧化硅的顶层。 第二氮含量高于第一氮含量，第二硅含量高于第一硅含量。

公开(公告)号：US06740920B2

公开(公告)日：2004-05-25

申请号：US10096219

申请日：2002-03-11

申请人： Dureseti Chidambarrao ,  Kil-Ho Lee ,  Jack A. Mandelman ,  Kevin McStay ,  Rajesh Rengarajan

发明人： Dureseti Chidambarrao ,  Kil-Ho Lee ,  Jack A. Mandelman ,  Kevin McStay ,  Rajesh Rengarajan

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L21/26586 ,  H01L27/10838 ,  H01L29/66666 ,  H01L29/7827

摘要： Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants—an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

摘要翻译： 在垂直MOSFET晶体管中的体效应显着降低，并且在具有在栅极处具有峰值的阈值注入的垂直晶体管中的其它器件参数不受影响，并且注入浓度分布从栅极快速下降到具有低p阱的平台 浓度值。 优选实施例采用两个体植入物 - 成角度的植入物，其在浇口处具有设置Vt的峰值，以及设置阱掺杂剂浓度的横向均匀的低剂量注入。

公开(公告)号：US6077734A

公开(公告)日：2000-06-20

申请号：US922358

申请日：1997-09-03

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L21/8232 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66575 ,  H01L21/2652 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/6659

摘要： The present invention is to provide a method for fabricating a semiconductor device which can minimize the defect density of the substrate, reduce the junction depth of the source/drain, and minimize the leakage current in the source/drain regions by implanting boron ions into the substrate in two steps which are different from each other by implant energy and implant dose.According to the invention, this method of fabricating semiconductor device comprises the steps of forming a gate oxide layer and a gate electrode on a semiconductor substrate or on a semiconductor substrate having N-well; implanting boron ions into the substrate at first and second ion implantation steps, the interstitial point defect region caused by the first ion implantation step overlapping with the vacancy point defect region caused by the second ion implantation step; and activating the boron implanted into the substrate by means of a subsequent thermal process to form source/drain regions.

摘要翻译： 本发明提供一种制造半导体器件的方法，其可以使衬底的缺陷密度最小化，减少源极/漏极的结深度，并且通过将硼离子注入到源极/漏极区域中来最小化源极/漏极区域中的漏电流 基板在两个步骤中通过植入能量和植入剂量彼此不同。 根据本发明，制造半导体器件的方法包括以下步骤：在半导体衬底上或在具有N阱的半导体衬底上形成栅极氧化物层和栅电极; 在第一和第二离子注入步骤中将硼离子注入到衬底中，由第一离子注入步骤引起的间隙点缺陷区域与由第二离子注入步骤引起的空位点缺陷区域重叠; 以及通过随后的热处理激活注入到衬底中的硼以形成源/漏区。

公开(公告)号：US5668020A

公开(公告)日：1997-09-16

申请号：US651856

申请日：1996-05-21

申请人： Kil Ho Lee

发明人： Kil Ho Lee

IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L29/08

CPC分类号： H01L29/6659 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0847 ,  Y10S148/061

摘要： A method for forming impurity junction regions of a semiconductor device wherein impurity junction regions with a small depth are formed by selectively forming defecting regions and amorphous regions in a semiconductor substrate by an implantation of impurity ions with a large molecular weight, thereby achieving an improvement in the characteristics of the semiconductor device. The method includes the steps of forming a first photoresist film pattern on an active region portion of a semiconductor substrate, implanting first impurity ions in exposed portions of said semiconductor substrate using said first photoresist film pattern as a mask, thereby forming defecting regions, removing said first photoresist film pattern, forming a second photoresist film pattern on the exposed semiconductor surface portions except for the portion which was covered with said first photoresist film pattern, implanting second impurity ions in exposed portions of said semiconductor substrate using said second photoresist film pattern as a mask, thereby forming amorphous regions, removing said second photoresist film pattern, and implanting third impurity ions in said active region portion of said semiconductor substrate, thereby forming impurity junction regions.

摘要翻译： 一种用于形成半导体器件的杂质结区的方法，其中通过以大分子量注入杂质离子选择性地在半导体衬底中形成缺陷区域和非晶区域，形成具有较小深度的杂质结区域，从而实现了改进 半导体器件的特性。 该方法包括以下步骤：在半导体衬底的有源区部分上形成第一光致抗蚀剂图案，使用所述第一光致抗蚀剂膜图案作为掩模，将所述半导体衬底的暴露部分中的第一杂质离子注入，从而形成缺陷区， 第一光致抗蚀剂膜图案，在暴露的半导体表面部分上形成第二光致抗蚀剂图案，除了被所述第一光致抗蚀剂膜图案覆盖的部分之外，使用所述第二光致抗蚀剂膜图案将所述第二光致抗蚀剂膜图案的第二杂质离子注入 从而形成非晶区域，去除所述第二光致抗蚀剂膜图案，以及在所述半导体衬底的所述有源区域部分中注入第三杂质离子，由此形成杂质结区域。

公开(公告)号：US09853087B2

公开(公告)日：2017-12-26

申请号：US15157403

申请日：2016-05-17

申请人： Ki-Seok Suh ,  Jae-Chul Shim ,  Kil-Ho Lee ,  Yong-Seok Chung ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

发明人： Ki-Seok Suh ,  Jae-Chul Shim ,  Kil-Ho Lee ,  Yong-Seok Chung ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC分类号： H01L27/22 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

公开(公告)号：US09356071B2

公开(公告)日：2016-05-31

申请号：US14804310

申请日：2015-07-20

申请人： Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

发明人： Bum-Seok Seo ,  Ki-Joon Kim ,  Kil-Ho Lee

IPC分类号： H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L21/311 ,  H01L29/82 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

公开(公告)号：US20150325625A1

公开(公告)日：2015-11-12

申请号：US14804310

申请日：2015-07-20

申请人： Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

发明人： Bum-Seok SEO ,  Ki-Joon KIM ,  Kil-Ho LEE

IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/02

CPC分类号： H01L27/228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

摘要翻译： 在基板上形成绝缘层。 在绝缘层上形成第一掩模。 第一掩模包括沿第二方向布置的多个线图案。 多个线图案沿着基本上垂直于第二方向的第一方向延伸。 在绝缘层和第一掩模上形成第二掩模。 第二掩模包括部分地暴露多个线图案的开口。 开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。 使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。 多个第一沟槽和第二沟槽以交错图案布置。

公开(公告)号：US20140377950A1

公开(公告)日：2014-12-25

申请号：US14285969

申请日：2014-05-23

申请人： Yong-Jun KIM ,  Kil-Ho LEE ,  Ki-Joon KIM ,  Myoung-Su SON

发明人： Yong-Jun KIM ,  Kil-Ho LEE ,  Ki-Joon KIM ,  Myoung-Su SON

IPC分类号： H01L21/768

CPC分类号： H01L21/76807

摘要： A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.

摘要翻译： 一种制造半导体器件的方法，包括形成模制层; 在成型层上形成镶嵌掩模层和掩模层; 通过蚀刻掩模层形成掩模层图案; 通过部分蚀刻镶嵌掩模层形成镶嵌图案; 在掩模层图案上形成镶嵌掩模层以埋藏镶嵌图案; 通过蚀刻镶嵌掩模层和掩模层图案形成部分地与镶嵌图案重叠的镶嵌图案; 通过去除由镶嵌图案暴露的掩模层图案的一部分来连接镶嵌图案和镶嵌图案; 在镶嵌掩模层上形成镶嵌掩模层，以埋藏镶嵌图案; 以及通过使用掩模层图案的剩余部分蚀刻镶嵌掩模层和模制层，在镶嵌图案之下形成沟槽。

公开(公告)号：US20140117560A1

公开(公告)日：2014-05-01

申请号：US14053932

申请日：2013-10-15

申请人： Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

发明人： Kil-Ho Lee ,  Se-Woong Park ,  Ki-Joon Kim

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/7681 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.

摘要翻译： 公开了一种半导体器件和形成半导体器件的方法。 在该方法中，在衬底上形成诸如绝缘中间层的层。 在该层中形成第一沟槽，并且在第一沟槽中形成掩模层。 掩模层具有从第一沟槽的底表面到掩模层的顶部的第一厚度。 图案化掩模层以形成至少部分地暴露第一沟槽的侧壁的掩模。 与第一沟槽的暴露的侧壁相邻的掩模的一部分具有小于第一厚度的第二厚度。 使用掩模作为蚀刻掩模蚀刻该层以形成第二沟槽。 第二沟槽与第一沟槽流体连通。 在第一沟槽和第二沟槽中形成导电图案。