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    Temperature sensor and memory device having same
    12.
    发明授权
    Temperature sensor and memory device having same 有权

    公开(公告)号：US12061125B2

    公开(公告)日：2024-08-13

    申请号：US17011864

    申请日：2020-09-03

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Chia-Ming Hu ,  Chung-Kuang Chen ,  Chia-Ching Li ,  Chien-Fu Huang

    IPC分类号： G01K7/42 ,  H10B43/40 ,  H10B51/40

    CPC分类号： G01K7/425 ,  H10B43/40 ,  H10B51/40

    摘要： An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.

    SEMICONDUCTOR STRUCTURE FOR 3D MEMORY AND MANUFACTURING METHOD THEREOF
    13.
    发明公开
    SEMICONDUCTOR STRUCTURE FOR 3D MEMORY AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240268112A1

    公开(公告)日：2024-08-08

    申请号：US18164623

    申请日：2023-02-06

    申请人： MACRONIX International Co., Ltd.

    发明人： Kuan-Yuan Shen ,  Chia-Jung Chiu

    IPC分类号： H10B43/27

    CPC分类号： H10B43/27

    摘要： Provided are a semiconductor structure for a 3D memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate having a memory array region and a staircase region, an insulating layer, a stacked structure and a vertical channel (VC) structure. The insulating layer is disposed on the substrate. The stacked structure is disposed on the insulating layer. The stacked structure includes first dielectric layers separated from each other, and the stacked structure in the staircase region has a staircase profile. The VC structure is disposed in the stacked structure in the memory array region and penetrates through the stacked structure. There is a vertical hole in the stacked structure and the insulating layer in the staircase region, and a third dielectric layer is filled in the vertical hole.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    15.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240243180A1

    公开(公告)日：2024-07-18

    申请号：US18153368

    申请日：2023-01-12

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： I-Chen Yang ,  Chun Liang Lu ,  Yung-Hsiang Chen ,  Yao-Wen Chang

    IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/66598

    摘要： A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IMC METHOD THEREOF
    16.
    发明公开
    IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IMC METHOD THEREOF 审中-公开

    公开(公告)号：US20240231623A9

    公开(公告)日：2024-07-11

    申请号：US18049303

    申请日：2022-10-25

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Wei-Chih CHIEN ,  Cheng-Lin SUNG ,  Hsiang-Lan LUNG

    IPC分类号： G06F3/06

    CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0673

    摘要： The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

    MEMORY DEVICE AND IN-MEMORY SEARCH METHOD THEREOF
    18.
    发明公开
    MEMORY DEVICE AND IN-MEMORY SEARCH METHOD THEREOF 审中-公开

    公开(公告)号：US20240221830A1

    公开(公告)日：2024-07-04

    申请号：US18173096

    申请日：2023-02-23

    申请人： MACRONIX International Co., Ltd.

    发明人： Po-Hao Tseng ,  Tian-Cih Bo ,  Feng-Min Lee

    IPC分类号： G11C15/04 ,  G11C16/04 ,  G11C16/26

    CPC分类号： G11C15/04 ,  G11C16/0483 ,  G11C16/26

    摘要： A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.

    Managing data refresh in semiconductor devices
    19.
    发明授权
    Managing data refresh in semiconductor devices 有权

    公开(公告)号：US12020741B2

    公开(公告)日：2024-06-25

    申请号：US17838921

    申请日：2022-06-13

    申请人： Macronix International Co., Ltd.

    发明人： Shuo-Nan Hung

    IPC分类号： G11C11/40 ,  G11C11/406 ,  G11C11/4096 ,  H03K19/20

    CPC分类号： G11C11/40615 ,  G11C11/40618 ,  G11C11/4096 ,  H03K19/20

    摘要： Methods, devices, and systems for managing data refresh for semiconductor devices are provided. In one aspect, a semiconductor device includes a memory cell array having a plurality of blocks each including multiple pages and one or more integrated circuits coupled to the memory cell array. The one or more integrated circuits are configured to: read specific data from a page of a block in the memory cell array, perform a logic operation on the specific data in the page to obtain a logic operation result, count a number of bits having a specific value among the logic operation result, determine whether the number of bits is within a data refresh criterion for the page, and in response to determining that the number of bits is outside of the data refresh criterion, generate a data refresh warning message for the page in the block.