公开(公告)号：US09105691B2

公开(公告)日：2015-08-11

申请号：US13859013

申请日：2013-04-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick C. Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/84 ,  H01L21/00 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76237 ,  H01L21/76897 ,  H01L21/84

Abstract: A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material.

Abstract translation: 一种形成绝缘体上半导体（SOI）器件的方法包括：在SOI衬底中限定浅沟槽隔离（STI）结构，所述SOI衬底包括体层，主体层上的埋层绝缘体（BOX）层，以及 BOX层上的SOI层; 在对应于STI结构的较低位置的本体层的一部分中形成掺杂区域，所述掺杂区域横向延伸到BOX层下面的体层中; 相对于本体层的未掺杂区域选择性地蚀刻本体层的掺杂区域，使得STI结构的较低位置切割BOX层; 并用绝缘体填充材料填充STI结构。

公开(公告)号：US20140302661A1

公开(公告)日：2014-10-09

申请号：US13859013

申请日：2013-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Laurent Grenouillet ,  Ali Khakifirooz ,  Yannick C. Le Tiec ,  Qing Liu ,  Maud Vinet

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/76237 ,  H01L21/76897 ,  H01L21/84

Abstract: A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material.

Abstract translation: 一种形成绝缘体上半导体（SOI）器件的方法包括：在SOI衬底中限定浅沟槽隔离（STI）结构，所述SOI衬底包括体层，主体层上的埋层绝缘体（BOX）层，以及 BOX层上的SOI层; 在对应于STI结构的较低位置的本体层的一部分中形成掺杂区域，所述掺杂区域横向延伸到BOX层下面的体层中; 相对于本体层的未掺杂区域选择性地蚀刻本体层的掺杂区域，使得STI结构的较低位置切割BOX层; 并用绝缘体填充材料填充STI结构。

公开(公告)号：US20150372104A1

公开(公告)日：2015-12-24

申请号：US14312418

申请日：2014-06-23

Applicant: STMICROELCTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US08889540B2

公开(公告)日：2014-11-18

申请号：US13778314

申请日：2013-02-27

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Qing Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/8238 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/785

Abstract: Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress.

Abstract translation: 具有记忆应力的晶体管和制造这种晶体管的方法。 所述方法包括形成具有沟道区，源极和漏极区以及栅极电介质的晶体管结构; 在所述晶体管结构的沟道区上沉积应力器，其中所述应力源向所述沟道区提供应力; 在应力存储在通道区域内之前去除应力金属; 以及在所述晶体管结构的沟道区域上沉积功函数金属，其中所述功函数金属对所述沟道区施加比由所述应力源施加的应力更小的应力。 具有记忆应力的晶体管包括衬底上的源区和漏区; 衬底上的应力记忆通道区域，其保持外部施加的应力; 以及包括与外部施加的应力相比对应力存储的沟道区域施加较小应力的功函栅极金属的栅极结构。

公开(公告)号：US20190259673A1

公开(公告)日：2019-08-22

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/161 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L21/266 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/265

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10319647B2

公开(公告)日：2019-06-11

申请号：US15890001

申请日：2018-02-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/161 ,  H01L29/423

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10256351B2

公开(公告)日：2019-04-09

申请号：US15723149

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/00 ,  H01L29/788 ,  H01L21/02

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10204982B2

公开(公告)日：2019-02-12

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

公开(公告)号：US10153371B2

公开(公告)日：2018-12-11

申请号：US14175215

申请日：2014-02-07

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

公开(公告)号：US20180239085A1

公开(公告)日：2018-08-23

申请号：US15962633

申请日：2018-04-25

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: G02B6/10 ,  G02B6/122 ,  G02B6/13 ,  C30B25/04 ,  C30B29/06 ,  C30B23/04 ,  G02B6/136 ,  G02B6/032 ,  G02B6/12

CPC classification number: G02B6/107 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/032 ,  G02B6/122 ,  G02B6/131 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.