公开(公告)号：US11355493B2

公开(公告)日：2022-06-07

申请号：US16858801

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Li-Feng Teng ,  Li-Jung Liu

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

公开(公告)号：US11348935B2

公开(公告)日：2022-05-31

申请号：US16869780

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US11217627B2

公开(公告)日：2022-01-04

申请号：US16886480

申请日：2020-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Jiun-Yu Tsai ,  Sheng-Huang Huang ,  Ming-Che Ku ,  Hung-Cho Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  H01L43/10

Abstract: A method of forming a MRAM device includes forming an interconnect structure spanning a memory region and a peripheral region; forming a MTJ stack over the interconnect structure within the memory region; depositing a dielectric layer over the MTJ stack and spanning the memory region and the peripheral region; removing a first portion of the dielectric layer from the peripheral region, while leaving a second portion of the dielectric layer within the memory region; after removing the first portion of the dielectric layer from the peripheral region, forming a first IMD layer spanning the memory region and the peripheral region; forming a dual damascene structure through the first IMD layer to a metallization pattern of the interconnect structure within the peripheral region; and after forming the dual damascene structure within the peripheral region, forming a top electrode via in contact with a top electrode of the MTJ stack.

公开(公告)号：US11152384B2

公开(公告)日：2021-10-19

申请号：US16387720

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11548 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/027

Abstract: An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.

公开(公告)号：US11139341B2

公开(公告)日：2021-10-05

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US11121308B2

公开(公告)日：2021-09-14

申请号：US16601723

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Chang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsung-Hsueh Yang ,  Yuan-Tai Tseng ,  Sheng-Huang Huang ,  Chia-Hua Lin

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.

公开(公告)号：US11056566B2

公开(公告)日：2021-07-06

申请号：US16705508

申请日：2019-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a sacrificial spacer over a substrate and forming a select gate along a side of the sacrificial spacer. An inter-gate dielectric is formed over the select gate and the sacrificial spacer. A memory gate layer is formed over the inter-gate dielectric and the sacrificial spacer. The memory gate layer is laterally separated from the sacrificial spacer by the select gate. The memory gate layer is etched to define a memory gate having a topmost point below a top of the sacrificial spacer.

公开(公告)号：US20210057639A1

公开(公告)日：2021-02-25

申请号：US16809998

申请日：2020-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Che KU ,  Jun-Yao CHEN ,  Sheng-Huang HUANG ,  Jiun-Yu TSAI ,  Harry-Hak-Lay Chuang ,  Hung-Cho Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A method of forming a magnetic random access memory (MRAM) device includes forming a bottom electrode layer over a substrate including an inter-metal dielectric (IMD) layer having a metal line therein; forming a barrier layer over the bottom electrode layer; forming a magnetic tunnel junction (MTJ) layer stack over the bottom electrode layer; forming a dielectric layer over the MTJ layer stack; forming an opening in the dielectric layer to expose the barrier layer; filling the opening in the dielectric layer with a top electrode; after filling the opening in the dielectric layer with the top electrode, etching the dielectric layer to expose the barrier layer; and patterning the MTJ layer stack to form an MTJ stack that exposes the bottom electrode layer.

公开(公告)号：US20200127047A1

公开(公告)日：2020-04-23

申请号：US16412714

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L43/12 ,  H01F41/32 ,  H01L21/768

Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.

公开(公告)号：US20200075669A1

公开(公告)日：2020-03-05

申请号：US16423276

申请日：2019-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.