-
公开(公告)号：US3781822A
公开(公告)日：1973-12-25
申请号：US3781822D
申请日：1972-08-09
发明人： AHAMED S
摘要： An input sequence of signals is processed by a cascaded plurality of stages, each stage including a plurality of unequal delay transmission paths, and means for directing selected portions of the input sequence through respective paths. By controlling the selection process at each stage, and by choosing suitable delay intervals, the rate of the input sequence may be increased or decreased by an integer factor and may be reversed in order. By combining various component circuits a fractional rate change may be effected.
摘要翻译： 信号的输入序列由级联的多级处理，每级包括多个不等延迟传输路径，以及用于通过相应路径引导输入序列的选定部分的装置。 通过控制每个阶段的选择过程，并且通过选择合适的延迟间隔，输入序列的速率可以增加或减少整数因子，并且可以按顺序颠倒。 通过组合各种组件电路，可以实现分数变化率。
-
公开(公告)号：US3778773A
公开(公告)日：1973-12-11
申请号：US3778773D
申请日：1972-10-20
发明人： HOOD D
摘要： A matrix of shift registers under the control of a plurality of gates for manipulating data information. The various functions which may be performed by the manipulator include serial-toparallel and parallel-to-serial conversion, serial-to-serial buffering and interleaving or separating streams of data information.
摘要翻译： 在用于操纵数据信息的多个门的控制下的移位寄存器的矩阵。 可以由机械手执行的各种功能包括串行到并行和并行到串行转换，串行到串行缓冲和交织或分离数据信息流。
-
公开(公告)号：US3766534A
公开(公告)日：1973-10-16
申请号：US3766534D
申请日：1972-11-15
申请人： IBM
发明人： BEAUSOLEIL W , PHELPS B
CPC分类号： G06F7/78 , G11C15/04 , G11C19/188 , G11C19/287
摘要： A data storage unit in which words of data including the word addresses are stored in groups of shiftable matrices, the groups of matrices being operable on a signal requesting access to repetitively shift their contents to other matrix positions in various loops, some of which include a position from which a word may be accessed and some of which exclude the access position. The bits in a data word are distributed among groups of matrices, each group generally containing only one bit of a given word. Each group is logically divided into a plurality of sectors, with each sector containing bits from several words. Controls are provided for varying the shifting in the various loops such that the positions of some or all of the sectors are dynamically reordered so that the proximity of each of the sectors to the access position is approximately or exactly the order in which the sectors were last requested, and so that the word bits within the sectors are also positioned so that their proximity to the access position is approximately or exactly the order in which they were last requested, thus reducing average access time in programs involving considerable repeated reference to a limited group of sectors and/or words in the memory, and substantially reducing worst-case access time for all situations.
摘要翻译： 一种数据存储单元，其中包括字地址的数据的字被存储在可移位矩阵的组中，所述矩阵组可以在请求访问的信号上操作以将它们的内容重复地移动到各种循环中的其他矩阵位置，其中一些包括 可以访问单词的位置，其中一些排除访问位置。 数据字中的位分布在矩阵组中，每组通常只包含给定字的一个位。 每组逻辑上划分为多个扇区，每个扇区包含来自多个单词的位。 提供控制以改变各种环路中的移位，使得部分或全部扇区的位置被动态重新排序，使得每个扇区到访问位置的接近度大致或恰好是扇区最后的顺序 并且使得扇区中的字位也被定位成使得它们与访问位置的接近度近似或恰好地是它们最后请求的顺序，从而减少涉及相当多地重复引用有限组的程序中的平均访问时间 的存储器中的扇区和/或字，并且大大减少了所有情况下的最坏情况访问时间。
-
-
公开(公告)号：US3226693A
公开(公告)日：1965-12-28
申请号：US19422062
申请日：1962-05-10
申请人： SPERRY RAND CORP
发明人： DUMEY ARNOLD I
CPC分类号： G06F7/78 , G06F7/768 , G06Q20/127 , G07F17/0014 , G11B27/10
-
公开(公告)号：US20240338175A1
公开(公告)日：2024-10-10
申请号：US18141917
申请日：2023-05-01
申请人： NVIDIA Corporation
摘要： Apparatuses, systems, and techniques to store tensor operands. In at least one embodiment, modes of one or more tensor operands are sorted based, at least in part, on one or more performance metrics of one or more tensor operations to be performed using said one or more tensor operands.
-
公开(公告)号：US20240232286A9
公开(公告)日：2024-07-11
申请号：US18076407
申请日：2022-12-07
申请人： NEUCHIPS CORPORATION
发明人： Chiung-Liang Lin , YuShan Ruan , Huan Jan Chou
CPC分类号： G06F17/16 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F7/78
摘要： A matrix computing device and an operation method for the matrix computing device are provided. The matrix computing device includes a storage unit, a control circuit, and a computing circuit. The storage unit includes a weight matrix. The control circuit re-orders an arrangement order of weights in the weight matrix according to a shape of an output matrix to determine a weight readout order of the weights. The computing circuit receives the weights based on the weight readout order, and performs a matrix computation on the weights and an input matrix to generate a computing matrix. The control circuit performs a reshape transformation on the computing matrix to generate the output matrix, and writes the output matrix to the storage unit.
-
公开(公告)号：US11972230B2
公开(公告)日：2024-04-30
申请号：US16914318
申请日：2020-06-27
申请人： Intel Corporation
发明人： Menachem Adelman , Robert Valentine , Barukh Ziv , Amit Gradstein , Simon Rubanovich , Zeev Sperber , Mark J. Charney , Christopher J. Hughes , Alexander F. Heinecke , Evangelos Georganas , Binh Pham
CPC分类号： G06F7/78 , G06F9/3001 , G06F9/3016 , G06F17/16
摘要： Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.
-
公开(公告)号：US11954583B2
公开(公告)日：2024-04-09
申请号：US18134726
申请日：2023-04-14
发明人： Jeffrey T Huynh , Vignesh Vivekraja
CPC分类号： G06N3/063 , G06F7/50 , G06F7/523 , G06F7/5443 , G06F7/78 , G06F9/5027 , G06F17/153
摘要： In one example, a neural network accelerator can execute a set of instructions to: load a first weight data element from a memory into a systolic array, the first weight data element having first coordinates; extract, from the instructions, information indicating a first subset of input data elements to be obtained from the memory, the first subset being based on a stride of a transposed convolution operation and second coordinates of first weight data element in a rotated array of weight data elements; based on the information, obtain the first subset of input data elements from the memory; load the first subset of input data elements into the systolic array; and control the systolic array to perform first computations based on the first weight data element and the first subset of input data elements to generate output data elements of an array of output data elements.
-
公开(公告)号：US20240095304A1
公开(公告)日：2024-03-21
申请号：US18382891
申请日：2023-10-23
申请人： Meta Platforms, Inc.
摘要： A system includes a matrix transpose component, a matrix processing component, a data modification component, and a data reduction component. The matrix transpose component is configured to transpose a stored matrix to an output matrix. The matrix processing component is configured to multiply the output matrix with a mask vector to determine a result vector. The data modification component is configured to modify at least a portion of the result vector to determine a modified vector. The data reduction component is configured to sum at least a portion of elements included in the modified vector.
-
-
-
-
-
-
-
-
-
搜索结果
205 条记录 (耗时 0.047 秒)
