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公开(公告)号：US20220365784A1
公开(公告)日：2022-11-17
申请号：US17824775
申请日：2022-05-25
申请人： Meta Platforms, Inc.
摘要： A processor system comprises a shared memory and a processing element. The processing element includes a matrix processor unit and is in communication with the shared memory. The processing element is configured to receive a processor instruction specifying a data matrix and a matrix manipulation operation. A manipulation matrix based on the processor instruction is identified. The data matrix and the manipulation matrix are used to perform a matrix operation to determine a result matrix.
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公开(公告)号：US11455143B2
公开(公告)日：2022-09-27
申请号：US16869281
申请日：2020-05-07
申请人： Meta Platforms, Inc.
摘要： A device (e.g., an integrated circuit chip) includes a dot product processing component, a data alignment component, and an accumulator. The dot product processing component is configured to calculate a dot product of a first group of elements stored in a first storage unit with a second group of elements, wherein: each element of the first group of elements is represented using a first number of bits, each value of a group of values stored in the first storage unit is represented using a second number of bits greater than the first number of bits, and each value of the group of values is stored as split segments across more than one element of the elements of the first group of elements. The data alignment component is configured to receive results of the dot product processing component and modify one or more of the results of the dot product processing component. The accumulator is configured to sum outputs of the data alignment component to at least in part determine a sum of the group of values.
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3.发明授权公开(公告)号：US11409838B2
公开(公告)日：2022-08-09
申请号：US16667791
申请日：2019-10-29
申请人： Meta Platforms, Inc.
发明人： Krishnakumar Narayanan Nair , Olivia Wu , Ehsan Khish Ardestani Zadeh , Abdulkadir Utku Diril , Thomas Mark Ulrich , Yuchen Hao , Rakesh Komuravelli , Aravind Kalaiah
摘要： A system comprises a data input vector unit, a weight input vector unit, and a plurality of calculation units of a matrix processor unit. The data input vector unit is configured to concurrently receive elements of different rows of a first and second data matrix. The weight input vector unit is configured to receive a combined weight vector and at least in part concurrently provide obtained weight elements of a first and second weight matrix to a corresponding first and second group of calculation units. Each calculation unit of the first and second group of calculation units is configured to multiply elements from the data input vector unit with elements of the corresponding weight matrix from the weight input vector unit and sum together multiplication results of the corresponding calculation unit to at least in part determine a corresponding element in a first or second convolution result matrix.
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公开(公告)号：US20240348263A1
公开(公告)日：2024-10-17
申请号：US18301816
申请日：2023-04-17
申请人： Meta Platforms, Inc.
发明人： Kaushal Gandhi , Olivia Wu , Soheil Gharahi , Thomas Mark Ulrich , Abdulkadir Utku Diril , Khasim S. Dudekula , Eda Sahin
IPC分类号： H03M7/42
CPC分类号： H03M7/42
摘要： Systems, apparatuses and methods provide technology that compresses first data based on a first compression scheme to generate second data, where the first data is associated with a first machine learning model. The technology stores the second data into a memory, adjusts a first entry of a lookup table to correspond to the first compression scheme based on the first data being compressed based on the first compression scheme, provide the second data from the memory to processing elements of a processing array during execution of the first machine learning model, and decompresses, at the processing array, the second data based on the lookup table to obtain the first data.
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公开(公告)号：US11520853B2
公开(公告)日：2022-12-06
申请号：US16805339
申请日：2020-02-28
申请人： Meta Platforms, Inc.
发明人： Krishnakumar Narayanan Nair , Rakesh Komuravelli , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
摘要： A processor system comprises two groups of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate matrix for each channel. Each register stores at least one data element from each matrix. The hardware channel convolution processor unit is configured to multiply each data element in a first and second portion of the first group of registers with a corresponding data element in the second group of registers to determine corresponding multiplication results and sum together the multiplication results for each specific channel to determine two corresponding channel convolution result data elements in a corresponding channel convolution result matrix.
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公开(公告)号：US11443013B2
公开(公告)日：2022-09-13
申请号：US16826697
申请日：2020-03-23
申请人： Meta Platforms, Inc.
发明人： Rakesh Komuravelli , Krishnakumar Narayanan Nair , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
摘要： A processor system comprises a hardware channel convolution processor unit and dot product processor unit. The channel convolution processor unit is configured to perform depthwise convolution, including by multiplying each data element of a first group of data elements of a convolution data matrix with a corresponding data element of a second group of data elements of a plurality of depthwise convolution weight matrices and summing together, for each specific channel, multiplication results corresponding to the specific channel to determine one corresponding result data element in a corresponding channel convolution result matrix to calculate a portion of depthwise convolution results. The dot product processor unit is configured to perform pointwise convolution, including applying pointwise weight matrices to the portion of depthwise convolution results to determine a portion of separable convolution results while at least another portion of the depthwise convolution results is being calculated by the processor system.
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公开(公告)号：US11372644B2
公开(公告)日：2022-06-28
申请号：US16708224
申请日：2019-12-09
申请人： Meta Platforms, Inc.
摘要： A processor system comprises a shared memory and a processing element. The processing element includes a matrix processor unit and is in communication with the shared memory. The processing element is configured to receive a processor instruction specifying a data matrix and a matrix manipulation operation. A manipulation matrix based on the processor instruction is identified. The data matrix and the manipulation matrix are loaded into the matrix processor unit and a matrix operation is performed to determine a result matrix. The result matrix is outputted to a destination location.
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公开(公告)号：US20240095304A1
公开(公告)日：2024-03-21
申请号：US18382891
申请日：2023-10-23
申请人： Meta Platforms, Inc.
摘要： A system includes a matrix transpose component, a matrix processing component, a data modification component, and a data reduction component. The matrix transpose component is configured to transpose a stored matrix to an output matrix. The matrix processing component is configured to multiply the output matrix with a mask vector to determine a result vector. The data modification component is configured to modify at least a portion of the result vector to determine a modified vector. The data reduction component is configured to sum at least a portion of elements included in the modified vector.
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公开(公告)号：US11829441B2
公开(公告)日：2023-11-28
申请号：US17834203
申请日：2022-06-07
申请人： Meta Platforms, Inc.
摘要： A device includes a matrix transpose component, a matrix processing component, a data alignment component, and a data reduction component. The matrix transpose component is configured to transpose an input matrix of elements to output an output matrix of the elements that have been transposed. The matrix processing component is configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix. The data alignment component is configured to modify at least a portion of elements of a result of the matrix processing component. The data reduction component is configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values.
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公开(公告)号：US11580192B2
公开(公告)日：2023-02-14
申请号：US16843645
申请日：2020-04-08
申请人： Meta Platforms, Inc.
发明人： Rakesh Komuravelli , Krishnakumar Narayanan Nair , Abdulkadir Utku Diril , Ehsan Khish Ardestani Zadeh , Yuchen Hao , Martin Schatz , Thomas Mark Ulrich , Olivia Wu , Anup Ramesh Kadkol , Amin Firoozshahian
摘要： A processor system comprises a plurality of processing elements. Each processing element includes a corresponding convolution processor unit configured to perform a portion of a groupwise convolution. The corresponding convolution processor unit determines multiplication results by multiplying each data element of a portion of data elements in a convolution data matrix with a corresponding data element in a corresponding groupwise convolution weight matrix. The portion of data elements in the convolution data matrix that are multiplied belong to different channels and different groups. For each specific channel of the different channels, the corresponding convolution processor unit sums together at least some of the multiplication results belonging to the same specific channel to determine a corresponding channel convolution result data element. The processing elements sum together a portion of the channel convolution result data elements from a group of different convolution processor units to determine a groupwise convolution result data element.
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