发明授权
US3781822A Data rate-changing and reordering circuits 失效
数据速率变化和再生电路

Data rate-changing and reordering circuits
摘要:
An input sequence of signals is processed by a cascaded plurality of stages, each stage including a plurality of unequal delay transmission paths, and means for directing selected portions of the input sequence through respective paths. By controlling the selection process at each stage, and by choosing suitable delay intervals, the rate of the input sequence may be increased or decreased by an integer factor and may be reversed in order. By combining various component circuits a fractional rate change may be effected.
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