公开(公告)号：US09043740B2

公开(公告)日：2015-05-26

申请号：US14048918

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: G06F17/50 ,  H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/32 ,  H01F41/30 ,  H01F41/32 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  B82Y25/00 ,  B82Y40/00 ,  G06F17/5068 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/309 ,  H01F41/32 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.

Abstract translation: 公开了一种磁性隧道接合装置及其制造方法。 在特定实施例中，非暂时计算机可读介质包括处理器可执行指令。 当处理器执行时，指令使处理器开始在磁隧道结结构的自由层上沉积封盖材料以形成覆盖层。 所述指令在由所述处理器执行时使得所述处理器开始所述封盖材料的第一层的氧化以形成氧化材料的第一氧化层。

公开(公告)号：US09041131B2

公开(公告)日：2015-05-26

申请号：US14246165

申请日：2014-04-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang

IPC: H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract translation: 形成磁性隧道结（MTJ）装置的方法包括在MTJ结构上形成第一MTJ盖层。 第一MTJ盖层包括第一非硝化金属。 该方法还包括在第一MTJ盖层上形成第二MTJ盖层。 第二MTJ盖层包括第二非硝化金属。 该方法还包括在第二MTJ盖层上形成顶部电极层。 第二MTJ盖层是导电的并且被配置为减少或防止氧化。

公开(公告)号：US08796046B2

公开(公告)日：2014-08-05

申请号：US14036354

申请日：2013-09-25

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L29/82 ,  G11C11/16 ,  H01L27/22 ,  H01L27/115 ,  H01L43/08

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L23/552 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.

Abstract translation: 提供了用于屏蔽屏蔽非易失性存储器的方法和装置，例如屏蔽磁性隧道结（MTJ）装置与磁通量。 在一个示例中，屏蔽层邻近MTJ器件的电极形成，使得屏蔽层基本上围绕电极的表面，并且金属线耦合到屏蔽层。 金属线可以通过通孔耦合到屏蔽层。

公开(公告)号：US20140098602A1

公开(公告)日：2014-04-10

申请号：US14104443

申请日：2013-12-12

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Xiaochun Zhu ,  Seung Hyuk Kang ,  Matthew Michael Nowak ,  Jeffrey Alexander Levin ,  Robert P. Gilmore ,  Nicholas Ka Ming Yu

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/54 ,  G11C11/5607

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract translation: 将概率编程电流注入到双稳定概率开关元件簇中，概率编程电流具有设置为导致任何给定双稳态开关元件切换的小于一概率的参数，以及bi的簇的电阻 - 检测到稳定的开关元件。 注入概率编程电流，并检测到簇状态的电阻，直到满足终止条件。 可选地，终止条件是以表示多位数据的值检测双稳态开关元件群的电阻。

公开(公告)号：US20140063933A1

公开(公告)日：2014-03-06

申请号：US14076427

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Hari M. Rao ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1693

Abstract: A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state.

Abstract translation: 第一写入驱动器将高于固定电位的第一电压施加到第一端子。 第二写入驱动器将比固定电位高于第一电压的第二电压施加到第二端子。 至少有一个磁隧道结（MTJ）结构在第一端处的第一端耦合到第一写入驱动器，并且在第二端处的第二端耦合到第二写入驱动器。 MTJ结构的第一侧接收第一电压，并且MTJ结构的第二侧接收地电压以从第一状态变为第二状态。 MTJ结构的第二面接收第二电压，并且MTJ结构的第一侧接收地电压以从第二状态变为第一状态。

公开(公告)号：US20140043924A1

公开(公告)日：2014-02-13

申请号：US14056990

申请日：2013-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Hari M. Rao ,  Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L43/12

CPC classification number: G11C11/1677 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/161 ,  G11C29/18 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/2602 ,  H01L43/12

Abstract: Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.

Abstract translation: 所公开的实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。 多行字线被排列成行。 多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。 存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。 位单元耦合到多个位线和多个源极线。 每个晶体管耦合到一个字线。 存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。

公开(公告)号：US20130320468A1

公开(公告)日：2013-12-05

申请号：US13959710

申请日：2013-08-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/10 ,  H01L43/12

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/12

Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

Abstract translation: 根据本发明的实施例，磁性隧道结（MTJ）元件包括参考铁磁层，存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

公开(公告)号：US11823052B2

公开(公告)日：2023-11-21

申请号：US16599306

申请日：2019-10-11

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Srivatsan Chellappa ,  Ramaprasath Vilangudipitchai ,  Seung Hyuk Kang

IPC: G06N3/082 ,  G06F7/544 ,  G06N3/063

CPC classification number: G06N3/082 ,  G06F7/5443 ,  G06N3/063

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for configuring a multiply-accumulate (MAC) block in an artificial neural network. A method generally includes receiving, at a neural processing unit comprising one or more logic elements, at least one input associated with a use-case of the neural processing unit; obtaining a set of weights associated with the at least one input; selecting a precision for the set of weights; modifying the set of weights based on the selected precision; and generating an output based, at least in part, on the at least one input, the modified set of weights, and an activation function.

公开(公告)号：US11290109B1

公开(公告)日：2022-03-29

申请号：US17030087

申请日：2020-09-23

Applicant: QUALCOMM Incorporated

Inventor： Foua Vang ,  Hyeokjin Lim ,  Seung Hyuk Kang ,  Venugopal Boynapalli ,  Shitiz Arora

IPC: H01L21/00 ,  H03K19/094 ,  H01L23/528

Abstract: A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mx layer interconnects on an Mx layer extending in a first direction over the first and second subcells. A first subset of the first set of Mx layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mx layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

公开(公告)号：US11237580B1

公开(公告)日：2022-02-01

申请号：US17015486

申请日：2020-09-09

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Foua Vang ,  Ramaprasath Vilangudipitchai ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC: G05F1/46 ,  H03K19/00 ,  H03K17/22

Abstract: A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.