公开(公告)号：US11601531B2

公开(公告)日：2023-03-07

申请号：US16702261

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Tsung-Yuan Tai

IPC: H04L69/22 ,  H04L43/08 ,  H04L47/35 ,  H04L1/00 ,  H04L67/568

Abstract: One embodiment provides a network system. The network system includes an application layer to execute one or more networking applications to generate or receive data packets having flow identification (ID) information; and a packet processing layer having profiling circuitry to generate a sketch table indicative of packet flow count data; the sketch table having a plurality of buckets, each bucket includes a first section including a plurality of data fields, each data field of the first section to store flow ID and packet count data, each bucket also having a second section having a plurality of data fields, each data field of the second section to store packet count data.

公开(公告)号：US11500825B2

公开(公告)日：2022-11-15

申请号：US16105031

申请日：2018-08-20

Applicant: INTEL CORPORATION

Inventor： Ren Wang ,  Bruce Richardson ,  Tsung-Yuan Tai ,  Yipeng Wang ,  Pablo De Lara Guarch

IPC: G06F16/21 ,  G06F16/22

Abstract: Techniques and apparatus for dynamic data access mode processes are described. In one embodiment, for example, an apparatus may a processor, at least one memory coupled to the processor, the at least one memory comprising an indication of a database and instructions, the instructions, when executed by the processor, to cause the processor to determine a database utilization value for a database, perform a comparison of the database utilization value to at least one utilization threshold, and set an active data access mode to one of a low-utilization data access mode or a high-utilization data access mode based on the comparison. Other embodiments are described.

公开(公告)号：US11409506B2

公开(公告)日：2022-08-09

申请号：US16142401

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Yipeng Wang ,  Ren Wang ,  Tsung-Yuan C. Tai ,  Jr-Shian Tsai ,  Xiangyang Guo

IPC: G06F9/44 ,  G06F9/445 ,  G06F11/36 ,  G06F8/41 ,  G06F9/455 ,  G06F8/30

Abstract: Examples may include a method of compiling a declarative language program for a virtual switch. The method includes parsing the declarative language program, the program defining a plurality of match-action tables (MATs), translating the plurality of MATs into intermediate code, and parsing a core identifier (ID) assigned to each one of the plurality of MATs. When the core IDs of the plurality of MATs are the same, the method includes connecting intermediate code of the plurality of MATs using function calls, and translating the intermediate code of the plurality of MATs into machine code to be executed by a core identified by the core IDs.

公开(公告)号：US11327894B2

公开(公告)日：2022-05-10

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20210367887A1

公开(公告)日：2021-11-25

申请号：US17396553

申请日：2021-08-06

Applicant: Intel Corporation

Inventor： Ren Wang ,  Tsung-Yuan C. Tai ,  Yipeng Wang ,  Sameh Gobriel

IPC: H04L12/743 ,  H04L12/851 ,  H04L12/741 ,  H04L29/12

Abstract: Apparatus, methods, and systems for tuple space search-based flow classification using cuckoo hash tables and unmasked packet headers are described herein. A device can communicate with one or more hardware switches. The device can include memory to store hash table entries of a hash table. The device can include processing circuitry to perform a hash lookup in the hash table. The lookup can be based on an unmasked key include in a packet header corresponding to a received data packet. The processing circuitry can retrieve an index pointing to a sub-table, the sub-table including a set of rules for handling the data packet. Other embodiments are also described.

公开(公告)号：US11068399B2

公开(公告)日：2021-07-20

申请号：US15720379

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bin Li ,  Chunhui Zhang ,  Ren Wang ,  Ram Huggahalli

IPC: G06F12/00 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/46 ,  H04L12/933 ,  H04L12/741 ,  H04L12/861

Abstract: Technologies for enforcing coherence ordering in consumer polling interactions include a network interface controller (NIC) of a target computing device which is configured to receive a network packet, write the payload of the network packet to a data storage device of the target computing device, and obtain, subsequent to having transmitted a last write request to write the payload to the data storage device, ownership of a flag cache line of a cache of the target computing device. The NIC is additionally configured to receive a snoop request from a processor of the target computing device, identify whether the received snoop request corresponds to a read flag snoop request associated with an active request being processed by the NIC, and hold the received snoop request for delayed return in response to having identified the received snoop request as the read flag snoop request. Other embodiments are described herein.

公开(公告)号：US11042403B2

公开(公告)日：2021-06-22

申请号：US15645226

申请日：2017-07-10

Applicant: INTEL CORPORATION

Inventor： Christopher B. Wilkerson ,  Karl I. Taht ,  Ren Wang ,  James J. Greensky ,  Tsung-Yuan C. Tai

IPC: G06F9/48 ,  G06F11/36 ,  G06F11/34

Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.

公开(公告)号：US10929323B2

公开(公告)日：2021-02-23

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F9/54 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US10724869B2

公开(公告)日：2020-07-28

申请号：US16166928

申请日：2018-10-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Zhonghong Ou ,  Arvind Kumar ,  Kristoffer Fleming ,  Tsung-Yuan C. Tai ,  Timothy J. Gresham ,  John C. Weast ,  Corey Kukis

IPC: G01C21/34 ,  H04W4/024 ,  H04W4/029 ,  H04B17/318 ,  H04W24/08 ,  H04W4/02 ,  H04W88/02

Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data.

公开(公告)号：US20200233664A1

公开(公告)日：2020-07-23

申请号：US16717258

申请日：2019-12-17

Applicant: Intel Corporation

Inventor： Ren Wang ,  Chunhui Zhang ,  Qixiong J. Bian ,  Bret L. Toll ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F12/128 ,  G06F12/0804 ,  G06F9/38 ,  G06F12/0811 ,  G06F13/28 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0842

Abstract: Method and apparatus for efficient range-based memory writeback is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.