公开(公告)号：US20190102302A1

公开(公告)日：2019-04-04

申请号：US15721223

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Karl I. Taht ,  Christopher B. Wilkerson ,  Ren Wang ,  James J. Greensky

IPC: G06F12/0831 ,  G06F12/0846 ,  G06F12/128

Abstract: Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.

公开(公告)号：US20190012200A1

公开(公告)日：2019-01-10

申请号：US15645226

申请日：2017-07-10

Applicant: INTEL CORPORATION

Inventor： Christopher B. Wilkerson ,  Karl I. Taht ,  Ren Wang ,  James J. Greensky ,  Tsung-Yuan C. Tai

IPC: G06F9/48

Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.

公开(公告)号：US10482017B2

公开(公告)日：2019-11-19

申请号：US15721223

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Karl I. Taht ,  Christopher B. Wilkerson ,  Ren Wang ,  James J. Greensky

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0846 ,  G06F12/128

Abstract: Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.

公开(公告)号：US11042403B2

公开(公告)日：2021-06-22

申请号：US15645226

申请日：2017-07-10

Applicant: INTEL CORPORATION

Inventor： Christopher B. Wilkerson ,  Karl I. Taht ,  Ren Wang ,  James J. Greensky ,  Tsung-Yuan C. Tai

IPC: G06F9/48 ,  G06F11/36 ,  G06F11/34

Abstract: A computing platform, including: an execution unit to execute a program, the program including a first phase and a second phase; and a quick response module (QRM) to: receive a program phase signature for the first phase; store the program phase signature in a pattern match action (PMA) table; identify entry of the program into the first phase via the PMA; and apply an optimization to the computing platform.