-
101.发明授权Nonvolatile memory with split substrate select gates and hierarchical bitline configuration 有权具有分离衬底选择门和分级位线配置的非易失性存储器公开(公告)号：US09007834B2
公开(公告)日：2015-04-14
申请号：US13830054
申请日：2013-03-14
发明人： Hyoung Seub Rhie
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.
摘要翻译： 通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。 本地位线耦合到每组存储器单元的存储单元。 每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。 选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。
-
公开(公告)号：US08946897B2
公开(公告)日：2015-02-03
申请号：US13826163
申请日：2013-03-14
发明人： Sang-Hyun Yi , Young-Nam Kim
IPC分类号： H01L29/40 , H01L23/528 , H01L21/822 , H01L27/06 , H01L27/11 , H01L27/115
CPC分类号： H01L23/562 , H01L21/8221 , H01L23/528 , H01L23/585 , H01L27/0688 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/1112 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.
摘要翻译： 包括半导体衬底，半导体衬底上的集成电路，覆盖集成电路的绝缘层和绝缘层上的多个金属线图案的半导体器件。 多个金属线图案的第一和第二相邻的金属线图案彼此间隔一个间隔，并且第一和第二相邻金属线图案中的每一个具有至少一个狭缝。
-
公开(公告)号：US08908378B2
公开(公告)日：2014-12-09
申请号：US13917728
申请日：2013-06-14
发明人： Jin-Ki Kim
CPC分类号： G06F1/16 , G06F3/0626 , G06F3/0658 , G06F3/0679 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/45014 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/00014 , H01L2924/14 , H05K3/284 , H05K2201/10159 , H05K2203/049 , H01L2224/45099 , H01L2924/00
摘要： A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.
摘要翻译： 公开了一种固态驱动器。 固态驱动器包括具有相对的第一和第二表面的电路板。 多个半导体芯片附接到固态驱动器的电路板的第一表面，并且固态驱动器的多个半导体芯片包括至少基本上封装在树脂中的至少一个存储器芯片。 还公开了一种在线存储器模块型形状电路板。 在线存储器模块型外形电路板具有相对的第一和第二表面。 多个半导体芯片附接到直列式存储模块型形状电路板的第一表面，并且这些半导体芯片包括至少基本上封装在树脂中的至少一个存储芯片。
-
公开(公告)号：US08898415B2
公开(公告)日：2014-11-25
申请号：US13962062
申请日：2013-08-08
发明人： Peter B. Gillingham
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0688 , G06F13/4243
摘要： A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.
摘要翻译： 用于布置存储器件的控制器可以发出写入命令而不等待先前发出的读取命令的接收。 寻址的存储器件可以根据读取命令将数据读出到数据总线上，同时根据读取命令之后接收的写入命令写入数据。
-
公开(公告)号：US20140307508A1
公开(公告)日：2014-10-16
申请号：US14046281
申请日：2013-10-04
发明人： Hyoung Seub Rhie
IPC分类号： G11C16/04
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/14 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.
摘要翻译： 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。
-
公开(公告)号：US08837237B2
公开(公告)日：2014-09-16
申请号：US14026359
申请日：2013-09-13
发明人： Jin-Ki Kim
摘要： A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
摘要翻译： 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。
-
公开(公告)号：US20140219664A1
公开(公告)日：2014-08-07
申请号：US13951058
申请日：2013-07-25
发明人： Marco ROMAGNOLI , Paola GALLI
IPC分类号： H04B10/556 , H04B10/2507
CPC分类号： H04B10/5563 , G02F2/00 , G02F2001/212 , G02F2202/20 , H04B10/25073 , H04B10/504
摘要： An optical communication system and method of use are described. The system comprises an optical source adapted to receive a digitally encoded data signal comprising sequences of data at a data rate (B) and comprising two signal levels representing a first state and a second state of the data signal, the optical source being adapted to produce an optical signal substantially frequency modulated with frequency excursion Δν comprising a first instantaneous frequency (ν0) associated to the first state and a second instantaneous frequency (ν1) associated to the second state; an optical converter adapted to receive the substantially frequency modulated optical signal, the optical converter having an optical transfer function varying with frequency and including at least one pass band, the at least one pass band having a peak transmittance and at least a low-transmittance region.
摘要翻译： 描述了光通信系统和使用方法。 该系统包括适于接收数字编码的数据信号的光源，该数字信号包括数据速率（B）的数据序列，并且包括表示数据信号的第一状态和第二状态的两个信号电平，光源适于产生 基本上频率调制的光信号与频率偏移＆Dgr; 包括与第一状态相关联的第一瞬时频率（＆ngr; 0）和与第二状态相关联的第二瞬时频率（＆ngr; 1） 光转换器，其适于接收基本上频率调制的光信号，所述光转换器具有随着频率变化并且包括至少一个通带的光传递函数，所述至少一个通带具有峰值透射率和至少低透射率区域 。
-
公开(公告)号：US20140170902A1
公开(公告)日：2014-06-19
申请号：US14083668
申请日：2013-11-19
发明人： Yehuda BINDER
IPC分类号： H01R31/00
CPC分类号： H01R31/005 , H01R31/065 , H04B3/542 , H04B2203/5425 , H04B2203/5437 , H04B2203/5441 , H04B2203/5445 , H04B2203/545 , H04B2203/5454 , H04B2203/5491 , H04B2203/5495 , H04L12/2856 , H04L12/2898 , H04N7/102 , H04N7/106 , H04Q11/04 , H04Q2213/13012 , H04Q2213/1308 , H04Q2213/13196 , H04Q2213/13199 , H04Q2213/13332 , H04Q2213/13389
摘要： In conjunction with a wiring in a house carrying data network signal, a modular outlet includes a base module and interface module. The base module connects to the wiring and is attached to the surface of a building. The interface module provides a data unit connection. The interface module is mechanically attached to the base module and electrically connected thereto. The wiring may also carry basic service signal such as telephone, electrical power and cable television (CATV). In such a case, the outlet provides the relevant connectivity either as part of the base module or as part of the interface module. Both proprietary and industry standard interfaces can be used to interconnect the module. Furthermore, a standard computer expansion card (such as PCI, PCMCIA and alike) may be used as interface module.
摘要翻译： 结合携带数据网络信号的房屋中的布线，模块化插座包括基座模块和接口模块。 基座模块连接到布线并连接到建筑物的表面。 接口模块提供数据单元连接。 接口模块机械连接到基座模块并与其电连接。 接线还可以承载电话，电力和有线电视（CATV）等基本业务信号。 在这种情况下，插座提供相关连接，作为基本模块的一部分或作为接口模块的一部分。 专有和行业标准接口均可用于互连模块。 此外，可以使用标准计算机扩展卡（例如PCI，PCMCIA等）作为接口模块。
-
109.再颁专利公开(公告)号：USRE44926E1
公开(公告)日：2014-06-03
申请号：US13774477
申请日：2013-02-22
发明人： Hong Beom Pyeon
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C5/04 , G11C7/10 , G11C7/1078 , G11C16/30
摘要： Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices.
摘要翻译： 将适配的块隔离方法应用于串行连接的存储器组件可以减轻串联连接的非易失性存储器件中的漏电流的影响。 响应于确定给定存储器组件不是命令的预期目的地，给定存储器组件的多个核心组件可以被置于低功耗模式中，同时将输入/输出组件保持在主动操作模式。 方便地，所公开的系统的方面减少了电流，而不会在存储器件中增加许多逻辑块。
-
公开(公告)号：US20140133243A1
公开(公告)日：2014-05-15
申请号：US14158215
申请日：2014-01-17
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G11C16/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
摘要翻译： 描述了用于存储器件的时钟模式配置电路。 存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。 可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。 每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从先前存储器件接收源同步时钟信号的串行模式。 根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。 通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。
-
-
-
-
-
-
-
-
-
搜索结果
184 条记录 (耗时 0.029 秒)
