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1457 条记录 (耗时 0.024 秒)

    PERIPHERAL CONTROLLER
    91.
    发明申请
    PERIPHERAL CONTROLLER 审中-公开

    公开(公告)号：US20170109314A1

    公开(公告)日：2017-04-20

    申请号：US15262746

    申请日：2016-09-12

    申请人： NXP B.V.

    发明人： VINOD KUMAR NAHVAL

    IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F5/06

    CPC分类号： G06F13/4291 ,  G06F5/065 ,  G06F13/4022 ,  G06F2205/067

    摘要： A peripheral controller, and method of operation, for half duplex communication between a system and a peripheral, in which a system clock and a peripheral clock are asynchronous, are described. A FIFO includes a FIFO controller and a FIFO memory and has a plurality of inputs. A multiplexer circuit is connected to the plurality of inputs, and is operable by a selection signal to supply either a first group of system and peripheral signals or a second group of system and peripheral signals to the FIFO to operate the FIFO to transmit data from the system to the peripheral or to receive data at the system from the peripheral.

    System and method for supporting a lazy sorting priority queue in a computing environment
    93.
    发明授权
    System and method for supporting a lazy sorting priority queue in a computing environment 有权
    用于在计算环境中支持懒惰排序优先级队列的系统和方法

    公开(公告)号：US09588733B2

    公开(公告)日：2017-03-07

    申请号：US14167792

    申请日：2014-01-29

    申请人： Oracle International Corporation

    发明人： Oleksandr Otenko

    IPC分类号： G06F13/20 ,  G06F5/06 ,  G06F9/52 ,  G06F9/54 ,  G06F13/22

    CPC分类号： G06F5/065 ,  G06F9/52 ,  G06F9/546 ,  G06F13/22 ,  G06F2205/067 ,  G06F2209/548 ,  G06F2213/2806

    摘要： A system and method can support queue processing in a computing environment. A lazy sorting priority queue in a concurrent system can include a priority queue and one or more buffers. The one or more buffers, which can be first-in first-out (FIFO) buffers, operate to store one or more requests received from one or more producers, and move at least one message to the priority queue when no consumer is waiting for processing a request. Furthermore, the priority queue operates to prioritize one or more incoming requests received from the one or more buffers, and allows one or more consumers to pick up the requests based on priority.

    摘要翻译： 系统和方法可以支持计算环境中的队列处理。 并发系统中的懒惰排序优先级队列可以包括优先级队列和一个或多个缓冲区。 一个或多个缓冲器，其可以是先进先出（FIFO）缓冲器，用于存储从一个或多个生产者接收到的一个或多个请求，并且当没有消费者等待时移动至少一个消息到优先级队列 处理请求。 此外，优先级队列用于对从一个或多个缓冲器接收到的一个或多个传入请求进行优先级排序，并允许一个或多个消费者基于优先级来接收请求。

    OPTIMIZING POWER IN A MEMORY DEVICE
    94.
    发明申请
    OPTIMIZING POWER IN A MEMORY DEVICE 有权
    优化存储器件中的电源

    公开(公告)号：US20170052584A1

    公开(公告)日：2017-02-23

    申请号：US15248364

    申请日：2016-08-26

    申请人： RAMBUS INC.

    发明人： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC分类号： G06F1/32 ,  G11C7/10 ,  G06F5/06 ,  G11C7/22

    CPC分类号： G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

    摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

    摘要翻译： 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

    Method and apparatus for calibrating write timing in a memory system
    95.
    发明授权
    Method and apparatus for calibrating write timing in a memory system 有权
    用于校准存储器系统中的写入定时的方法和装置

    公开(公告)号：US09552865B2

    公开(公告)日：2017-01-24

    申请号：US14931513

    申请日：2015-11-03

    申请人： Rambus Inc.

    发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

    IPC分类号： G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409 ,  G11C11/4096

    CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

    摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

    摘要翻译： 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

    Transmitting LSB timestamp datum in parallel and MSB in series
    96.
    发明授权
    Transmitting LSB timestamp datum in parallel and MSB in series 有权
    并行发送LSB时间戳数据，MSB串行发送

    公开(公告)号：US09536025B2

    公开(公告)日：2017-01-03

    申请号：US14547866

    申请日：2014-11-19

    申请人： Texas Instruments Incorporated

    发明人： Gary L. Swoboda

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F17/50 ,  G06F13/38 ,  G06F1/14

    CPC分类号： G06F17/5031 ,  G06F1/04 ,  G06F1/14 ,  G06F13/38 ,  G06F2217/14 ,  G06F2217/62 ,  G06F2217/84 ,  Y02T10/82

    摘要： A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are transmitted to a client via a parallel data bus. The most significant bits are transmitted to the client sequentially via a series data bus. Each client receives the parallel least significant bits and the series most significant bits and assembles a complete time stamp value.

    摘要翻译： 时间戳生成器生成具有预定数量的最高有效位和预定数量的最低有效位的时间戳值。 最低有效位通过并行数据总线传输到客户端。 最高有效位通过串行数据总线顺序发送给客户端。 每个客户端接收并行最低有效位和串行最高有效位，并组合一个完整的时间戳值。

    FIFO MEMORY HAVING A MEMORY REGION MODIFIABLE DURING OPERATION
    98.
    发明申请
    FIFO MEMORY HAVING A MEMORY REGION MODIFIABLE DURING OPERATION 有权
    具有可操作的存储区域的FIFO存储器

    公开(公告)号：US20160342390A1

    公开(公告)日：2016-11-24

    申请号：US15157989

    申请日：2016-05-18

    申请人： Robert Bosch GmbH

    发明人： Timo Giesselmann ,  Konstantin Buck ,  Rainer Dorsch

    IPC分类号： G06F5/06 ,  G06F5/14

    CPC分类号： G06F5/06 ,  G06F5/065 ,  G06F5/14 ,  G06F2205/063 ,  G06F2205/066 ,  G06F2205/126

    摘要： A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.

    摘要翻译： 具有可修改存储区域的FIFO存储器; FIFO存储器被配置为线性存储器和循环缓冲器; FIFO存储器具有状态机，其包含用于定义将来分配的存储器区域的新的基本值和新的顶部值，该区域的下边界由新的基本值定义，并且其上限被定义 通过新的顶部值，并且状态机被配置为使得在FIFO存储器的读取模式和/或写入模式中，FIFO存储器的分配的存储器区域可通过将基准指针移动到新的 基础值，和/或通过将顶部指针移动到新的顶部值。

    Memory card and communication method between a memory card and a host unit
    99.
    发明授权
    Memory card and communication method between a memory card and a host unit 有权
    存储卡和存储卡与主机之间的通信方法

    公开(公告)号：US09495629B2

    公开(公告)日：2016-11-15

    申请号：US12974179

    申请日：2010-12-21

    申请人： Alok Kumar Mittal ,  Deepak Naik

    发明人： Alok Kumar Mittal ,  Deepak Naik

    IPC分类号： G06F5/06 ,  G06K19/077 ,  G06F3/06

    CPC分类号： G06K19/07732 ,  G06F3/0661 ,  G06F5/06 ,  G06F2213/3804 ,  G06F2213/3852

    摘要： A memory card and a communication method between a memory card and a host unit are disclosed. High throughput of data between the memory card and the host unit is guaranteed by providing a communication interface between the memory card and the host unit including a first communication interface between a memory unit of the memory card and a control unit of the memory card and a second communication interface between the control unit of the memory card and the host unit.

    摘要翻译： 公开了一种存储卡和存储卡与主机之间的通信方法。 通过提供存储卡和主机单元之间的通信接口来保证存储卡和主机单元之间的高吞吐量，包括存储卡的存储器单元和存储卡的控制单元之间的第一通信接口和 存储卡的控制单元与主机单元之间的第二通信接口。