公开(公告)号：US20180292454A1

公开(公告)日：2018-10-11

申请号：US15944244

申请日：2018-04-03

申请人： Cypress Semiconductor Corporation

发明人： Harold M. Kutz ,  Timothy John Williams ,  Bert S. Sullam ,  Warren S. Snyder ,  James H. Shutt ,  Bruce E. Byrkett ,  Monte Mar ,  Eashwar Thiagarajan ,  Nathan Wayne Kohagen ,  David G. Wright ,  Mark E Hastings ,  Dennis R. Seguine

IPC分类号： G01R31/3177 ,  G06F13/28 ,  H03K19/173 ,  G01R31/317

CPC分类号： G01R31/3177 ,  G01R31/31721 ,  G06F13/28 ,  H03K19/173

摘要： A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

公开(公告)号：US20160065216A1

公开(公告)日：2016-03-03

申请号：US14668984

申请日：2015-03-26

申请人： Cypress Semiconductor Corporation

发明人： Eashwar Thiagarajan ,  Harold M. Kutz ,  Hans Klein ,  Jaskarn Singh Johal ,  Jean-Paul Vanitegem ,  Kendall V. Castor-Perry ,  Mark E. Hastings ,  Amsby D. Richardson, JR. ,  Anasuya Pai Maroor ,  Ata Khan ,  Dennis R. Seguine ,  Bruce E. Byrkett ,  Carl Ferdinand Liepold ,  Hans Van Antwerpen

IPC分类号： H03K19/0175 ,  H03M1/38 ,  H03K19/003 ,  H03K19/00

CPC分类号： H03K19/017581 ,  H03K19/0005 ,  H03K19/00346 ,  H03K19/02 ,  H03M1/1205 ,  H03M1/38

摘要： An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

摘要翻译： 集成电路（IC）装置可以包括多个模拟块，包括至少一个固定功能的模拟电路和至少一个可重新配置的模拟电路块，所述至少一个可重新配置的模拟电路块选自：包括多个可重新配置的放大器电路的连续时间（CT） 离散时间块，包括具有可重新配置的交换网络的放大器; 模拟多路复用器（MUX）被配置为选择性地将IC器件的多个输入/输出（I / O）中的任一个连接到模拟块，模拟MUX包括至少一个具有比其他电阻低的电阻的低噪声信号路径对 模拟MUX的信号路径; 至少一个模拟路由块可重新配置以提供任何模拟块之间的信号路径; 包括数字电路的数字部分; 以及耦合到模拟块的处理器接口。

公开(公告)号：US11088692B2

公开(公告)日：2021-08-10

申请号：US16862043

申请日：2020-04-29

申请人： Cypress Semiconductor Corporation

发明人： Timothy John Williams ,  David G. Wright ,  Gregory John Verge ,  Bruce E. Byrkett

IPC分类号： H03K19/0175 ,  G06F13/28 ,  G11C16/10 ,  G11C7/10 ,  G06F5/06 ,  G06F12/02 ,  G06F13/40

摘要： A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

公开(公告)号：US20190214990A1

公开(公告)日：2019-07-11

申请号：US16193261

申请日：2018-11-16

申请人： Cypress Semiconductor Corporation

发明人： Timothy John Williams ,  David G. Wright ,  Gregory John Verge ,  Bruce E. Byrkett

IPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C16/10 ,  G06F5/06 ,  G06F13/28 ,  G06F12/02

摘要： A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

公开(公告)号：US20170194963A1

公开(公告)日：2017-07-06

申请号：US15369674

申请日：2016-12-05

申请人： Cypress Semiconductor Corporation

发明人： Timothy John Williams ,  David G. Wright ,  Gregory John Verge ,  Bruce E. Byrkett

IPC分类号： H03K19/0175 ,  G06F13/28 ,  G11C7/10

CPC分类号： H03K19/017581 ,  G06F5/065 ,  G06F12/0246 ,  G06F13/28 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/102 ,  H03K19/01759

摘要： A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

公开(公告)号：US20160006439A1

公开(公告)日：2016-01-07

申请号：US14690106

申请日：2015-04-17

申请人： Cypress Semiconductor Corporation

发明人： Timothy John Williams ,  David G. Wright ,  Gregory John Verge ,  Bruce E. Byrkett

IPC分类号： H03K19/0175 ,  G11C16/10 ,  G06F13/28 ,  G06F12/02

CPC分类号： H03K19/017581 ,  G06F5/065 ,  G06F12/0246 ,  G06F13/28 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/102 ,  H03K19/01759

摘要： A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the TO pads.

摘要翻译： 一种具有处理系统和与处理系统和两个IO垫中的一个耦合的输入缓冲器的装置以及耦合到输入缓冲器和第二IO垫两者的参考缓冲器，使得参考发生器控制输入阈值 的响应于从第二TO焊盘上的外部电路接收的模拟电压的输入缓冲器。

公开(公告)号：US11105851B2

公开(公告)日：2021-08-31

申请号：US16821555

申请日：2020-03-17

申请人： Cypress Semiconductor Corporation

发明人： Harold Kutz ,  Timothy John Williams ,  Bert Sullam ,  Warren S. Snyder ,  James H. Shutt ,  Bruce E. Byrkett ,  Monte Mar ,  Eashwar Thiagarajan ,  Nathan Wayne Kohagen ,  David G. Wright ,  Mark E Hastings ,  Dennis R. Seguine

IPC分类号： G01R31/3177 ,  G06F13/28 ,  H03K19/173 ,  G01R31/317

摘要： A microcontroller comprises a plurality of digital peripheral blocks and a direct memory access (DMA) controller coupled thereto. The plurality of digital peripheral blocks includes a digital peripheral block that is configured to issue a DMA request. Upon receipt of the DMA request, the DMA controller is configured to retrieve configuration information and to write the configuration information to a configuration register associated with a circuit element of the microcontroller.

公开(公告)号：US20200321963A1

公开(公告)日：2020-10-08

申请号：US16862043

申请日：2020-04-29

申请人： Cypress Semiconductor Corporation

发明人： Timothy John Williams ,  David G. Wright ,  Gregory John Verge ,  Bruce E. Byrkett

IPC分类号： H03K19/0175 ,  G06F5/06 ,  G06F12/02 ,  G06F13/28 ,  G11C16/10 ,  G11C7/10

摘要： A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

公开(公告)号：US10345377B2

公开(公告)日：2019-07-09

申请号：US15944244

申请日：2018-04-03

申请人： Cypress Semiconductor Corporation

发明人： Harold M. Kutz ,  Timothy John Williams ,  Bert S. Sullam ,  Warren S. Snyder ,  James H. Shutt ,  Bruce E. Byrkett ,  Monte Mar ,  Eashwar Thiagarajan ,  Nathan Wayne Kohagen ,  David G. Wright ,  Mark E. Hastings ,  Dennis R. Seguine

IPC分类号： G06F13/28 ,  G01R31/317 ,  H03K19/173 ,  G01R31/3177

摘要： A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.

公开(公告)号：US09952282B1

公开(公告)日：2018-04-24

申请号：US14860515

申请日：2015-09-21

申请人： Cypress Semiconductor Corporation

发明人： Harold M. Kutz ,  Timothy John Williams ,  Bert S. Sullam ,  Warren S. Snyder ,  James H. Shutt ,  Bruce E. Byrkett ,  Monte Mar ,  Eashwar Thiagarajan ,  Nathan Wayne Kohagen ,  David G. Wright ,  Mark E Hastings ,  Dennis R. Seguine

IPC分类号： H03K19/173 ,  G01R31/3177 ,  G01R31/317

CPC分类号： G01R31/3177 ,  G01R31/31721 ,  G06F13/28 ,  H03K19/173

摘要： A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.