公开(公告)号：US09178000B1

公开(公告)日：2015-11-03

申请号：US14264280

申请日：2014-04-29

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Federico Nardi ,  Ryan C. Clarke ,  Tim Minvielle ,  Yun Wang

IPC: H01L29/02 ,  H01L29/792 ,  H01L27/11 ,  H01L21/00 ,  H01L27/24 ,  H01L45/00 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L27/2463 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L27/2436 ,  H01L29/0847 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells having extended conductive layers operable as electrodes of other devices, and methods of fabricating such cells and other devices. A conductive layer of a ReRAM cell extends beyond the cell boundary defined by the variable resistance layer. The extended portion may be used a source or drain region of a FET that may control an electrical current through the cell or other devices. The extended conductive layer may be also operable as electrode of another resistive-switching cell or a different device. The extended conductive layer may be formed from doped silicon. The variable resistance layer of the ReRAM cell may be positioned on the same level as a gate dielectric layer of the FET. The variable resistance layer and the gate dielectric layer may have the same thickness and share common materials, though they may be differently doped.

Abstract translation: 提供了具有可操作为其他器件的电极的延伸导电层的电阻随机存取存储器（ReRAM）单元，以及制造这样的单元和其它器件的方法。 ReRAM单元的导电层延伸超过由可变电阻层限定的单元边界。 延伸部分可以用于可控制通过电池或其他装置的电流的FET的源极或漏极区域。 扩展导电层也可以作为另一电阻式开关电池或不同器件的电极工作。 延伸的导电层可以由掺杂的硅形成。 ReRAM单元的可变电阻层可以位于与FET的栅极电介质层相同的水平上。 可变电阻层和栅极电介质层可以具有相同的厚度并且共享共同的材料，尽管它们可以是不同的掺杂。

公开(公告)号：US09177761B2

公开(公告)日：2015-11-03

申请号：US12860118

申请日：2010-08-20

Applicant: Shunpei Yamazaki

Inventor： Shunpei Yamazaki

IPC: C30B21/02 ,  H01J37/32 ,  C23C16/455 ,  C23C16/509 ,  H01L29/04 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01J37/32449 ,  C23C16/45565 ,  C23C16/5096 ,  H01J37/3244 ,  H01J37/32541 ,  H01J37/32834 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

Abstract: A structure of a plasma CVD apparatus for forming a dense semiconductor film is provided. Further, a technique for forming a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains is provided. An electrode supplied with electric power for generating plasma is included in a reaction chamber of the plasma CVD apparatus. This electrode has a common plane on a surface opposite to a substrate, and the common plane is provided with depressed openings. Gas supply ports are provided on the bottom of the depressed openings or on the common plane of the electrode. The depressed openings are provided in isolation from one another.

Abstract translation: 提供了用于形成致密半导体膜的等离子体CVD装置的结构。 此外，提供了在晶粒之间形成没有空腔的致密结晶半导体膜（例如微晶半导体膜）的技术。 在等离子体CVD装置的反应室中包含提供有用于产生等离子体的电力的电极。 该电极在与基板相反的表面上具有公共平面，并且公共平面设置有凹陷开口。 气体供给口设置在凹陷开口的底部或电极的共同平面上。 凹陷的开口彼此隔开设置。

公开(公告)号：US09129681B2

公开(公告)日：2015-09-08

申请号：US13733046

申请日：2013-01-02

Applicant: SanDisk Technologies Inc.

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/08 ,  H01L29/66 ,  H01L29/786 ,  G11C16/04 ,  G11C16/06 ,  H01L21/04 ,  H01L21/265 ,  H01L29/423 ,  H01L27/115 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L29/66757 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/04 ,  H01L21/26513 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1222 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

Abstract: Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole.

Abstract translation: 本文公开了薄膜晶体管（TFT）和用于制造TFT的技术。 TFT的栅电极的主平面可以相对于TFT所在的水平多晶硅层垂直取向。 栅极电极和栅极电介质之间的界面可以相对于TFT所在的水平多晶硅层垂直取向。 TFT可以具有由多晶硅的水平层的厚度限定的沟道宽度。 TFT可以通过蚀刻多晶硅层中的孔而形成。 然后，可以通过在侧壁上沉积电介质和导体材料层而在孔中形成栅电极和栅极电介质。 主体可以形成在孔外的多晶硅的水平层中。

公开(公告)号：US09123827B2

公开(公告)日：2015-09-01

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20150200142A1

公开(公告)日：2015-07-16

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US09082615B2

公开(公告)日：2015-07-14

申请号：US14235764

申请日：2013-11-18

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Xiang Zhang

IPC: H01L21/36 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02595 ,  H01L21/02636 ,  H01L21/02675

Abstract: The present invention provides a polysilicon manufacturing method that controls a growth direction of polysilicon, including the following steps: (1) forming a first buffer layer (20) on a substrate (10) through deposition; (2) applying a masking operation to form a lens-like structure (22) on a surface of the first buffer layer (20); (3) depositing and forming an amorphous silicon layer (40) on the first buffer layer (20) of which the surface comprises the lens-like structure (22) formed thereon; (4) subjecting the amorphous silicon layer (40) to rinsing; (5) irradiating the amorphous silicon layer (40) with an intense light (50) from the side of the substrate (10) so as to generate a crystal seed at a bottom of the amorphous silicon layer (40); and (6) applying a laser annealing operation to the amorphous silicon layer (40) that comprises a crystal seed generated therein so as to have amorphous silicon contained in the amorphous silicon layer (40) crystallized and forming a polysilicon layer (70). The present invention enables control of the growth direction of polysilicon.

Abstract translation: 本发明提供一种控制多晶硅生长方向的多晶硅制造方法，包括以下步骤：（1）通过沉积在基板（10）上形成第一缓冲层（20）; （2）在第一缓冲层（20）的表面上施加掩模操作以形成透镜状结构（22）; （3）在其上形成有透镜状结构（22）的第一缓冲层（20）上沉积和形成非晶硅层（40） （4）对非晶硅层（40）进行漂洗; （5）从所述基板（10）的一侧用强光（50）照射所述非晶硅层（40），以在所述非晶硅层（40）的底部产生晶种; 和（6）对包含在其中产生的晶种的非晶硅层（40）施加激光退火操作，以使非晶硅层（40）中包含的非晶硅结晶并形成多晶硅层（70）。 本发明能够控制多晶硅的生长方向。

公开(公告)号：US20150187575A1

公开(公告)日：2015-07-02

申请号：US14580566

申请日：2014-12-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yuhei Sato ,  Yasumasa Yamane ,  Yoshinori Yamada ,  Tetsunori Maruyama

IPC: H01L21/02 ,  C23C14/35 ,  C23C14/34

CPC classification number: H01L21/02631 ,  C23C14/08 ,  C23C14/086 ,  C23C14/3414 ,  C23C14/35 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of forming an oxide semiconductor includes a step of depositing an oxide semiconductor layer over a substrate by using a sputtering apparatus in which in a target containing indium, an element M (aluminum, gallium, yttrium, or tin), zinc, and oxygen, the substrate which faces a surface of the target, and a magnet unit comprising a first magnet and a second magnet on a rear surface side of the target are provided. In the method, deposition is performed under a condition that a maximum intensity of a horizontal magnetic field is greater than or equal to 350 G and less than or equal to 2000 G in a plane where a vertical distance toward the substrate from a surface of the magnet unit is 10 mm.

Abstract translation: 形成氧化物半导体的方法包括通过使用溅射装置在衬底上沉积氧化物半导体层的步骤，其中在含有铟的元素M（铝，镓，钇或锡），锌和氧元素 设置面向靶的表面的基板，以及在靶的背面侧具有第一磁体和第二磁体的磁体单元。 在该方法中，在水平磁场的最大强度大于或等于350G且小于或等于2000G的条件下，在从基板的表面垂直距离的平面中进行沉积 磁体单位为10 mm。

公开(公告)号：US20150171227A1

公开(公告)日：2015-06-18

申请号：US14133521

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/26

CPC classification number: H01L29/78693 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02538 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02631 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. The IGZO channel layer has a first sub-layer including c-IGZO and a second sub-layer including a-IGZO. A source electrode and a drain electrode are formed above the IGZO channel layer.

Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 在栅电极上方形成IGZO沟道层。 IGZO沟道层具有包括c-IGZO的第一子层和包括-IGZO的第二子层。 源电极和漏极形成在IGZO沟道层上方。

公开(公告)号：US20150170976A1

公开(公告)日：2015-06-18

申请号：US14407255

申请日：2013-06-13

Applicant: Shin-Etsu Chemical Co., Ltd.

Inventor： Kazunori Funazaki ,  Kazuomi Sato ,  Shuichi Miyao

IPC: H01L21/66 ,  G01N33/00 ,  H01L21/02

CPC classification number: H01L22/10 ,  C01B33/03 ,  C01B33/035 ,  G01N33/00 ,  G01N2033/0095 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262

Abstract: The present invention provides technology for realizing higher purification of a polycrystalline silicon. First, trichlorosilane is prepared as a sample (S101) and then the carbon-containing impurities content in the trichlorosilane is analyzed by GC/MS-SIM method (S102). The quality of the trichlorosilane is determined based on the analysis results (S103) and the trichlorosilane determined to be a good material (S103: Yes) is used as the raw material for producing a high-purity polycrystalline silicon by CVD method (104). In case, the trichlorosilane determined to be a bad material (S103: No) is not used as the raw material for producing a polycrystalline silicon. When the impurities analysis by GC/MS-SIM method is performed using, as a separation column, a column having a non-polar column and a medium-polar column connected in series with each other, it is possible to simultaneously perform both of the separation of chlorosilanes and hydrocarbons and the separation of chlorosilanes and methylsilanes.

Abstract translation: 本发明提供了实现多晶硅更高纯化的技术。 首先，作为样品制备三氯硅烷（S101），然后通过GC / MS-SIM法分析三氯硅烷中的含碳杂质含量（S102）。 基于分析结果确定三氯硅烷的质量（S103），将通过CVD法制造高纯度多晶硅的原料（104）用作为高质量的三氯硅烷（S103：是）。 判定为不良物质的三氯硅烷（S103：否）不用作多晶硅的制造原料。 当通过GC / MS-SIM方法进行杂质分析时，使用具有非极性列和中极性列的列作为分离柱进行串联连接，可以同时进行 分离氯硅烷和烃类以及氯硅烷和甲基硅烷的分离。

公开(公告)号：US09059030B2

公开(公告)日：2015-06-16

申请号：US13269304

申请日：2011-10-07

Applicant: Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

Inventor： Kamal M. Karda ,  Suraj J. Mathew ,  Jaydip Guha

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10832 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/28525 ,  H01L27/10861 ,  H01L27/10873 ,  H01L29/945

Abstract: A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.

Abstract translation: 存储单元包括晶体管器件，其包括一对源极/漏极，包括沟道的主体以及可操作地接近沟道的栅极结构。 存储单元包括电容器，该电容器包括一对在其间具有电容器电介质的电容器电极。 电容器电极之一是通道或电耦合到通道。 电容器电极中的另一个包括主体而不是通道的一部分。 还公开了方法。