公开(公告)号：US20140198572A1

公开(公告)日：2014-07-17

申请号：US14088127

申请日：2013-11-22

Applicant: CHANGHYUN LEE ,  SUNG-MIN HWANG

Inventor： CHANGHYUN LEE ,  SUNG-MIN HWANG

IPC: H01L23/50 ,  G11C16/08

CPC classification number: H01L23/50 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.

Abstract translation: 三维半导体器件包括彼此堆叠的第一和第二选择线。 水平地横越第一和第二选择线的上线。 第一和第二垂直图案垂直地跨越第一和第二选择线。 第一和第二垂直图案共同连接到上线。 第一和第二垂直图案中的每一个构成彼此串联连接的第一和第二选择晶体管。 第一和第二垂直图案的第一选择晶体管分别由第一和第二选择线控制。

公开(公告)号：US20140192596A1

公开(公告)日：2014-07-10

申请号：US13830054

申请日：2013-03-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub RHIE

IPC: G11C16/02

CPC classification number: G11C11/5635 ,  G11C16/0483 ,  G11C16/14

Abstract: Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.

Abstract translation: 通常，本公开提供了一种具有分级位线结构的非易失性存储器件，用于防止施加到存储器阵列的一组存储器单元的擦除电压泄漏到不需要擦除的其他组。 本地位线耦合到每组存储器单元的存储单元。 每个本地位线可以在所选择的组的读取操作期间选择性地连接到全局位线，并且当选择特定组以进行擦除时，在擦除操作期间，可以将全局位线与全局位线断开。 选择用于将特定组存储器单元的每个位线电连接到全局位线的器件具有与这些存储器单元的主体电隔离的器件体。

公开(公告)号：US20140169095A1

公开(公告)日：2014-06-19

申请号：US13801800

申请日：2013-03-13

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Chris Nga Yee Avila ,  Yingda Dong ,  Man Lung Mui

IPC: G11C16/34

CPC classification number: G11C16/107 ,  G11C11/5635 ,  G11C16/24 ,  G11C16/3404 ,  G11C29/02 ,  G11C29/024 ,  G11C29/028 ,  G11C2029/0409

Abstract: In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

Abstract translation: 在其中选择晶体管包括电荷存储元件的非易失性存储器阵列中，监视选择晶体管的阈值电压，并且如果阈值电压偏离期望的阈值电压范围，则将电荷添加到电荷存储器 元件将阈值电压返回到期望的阈值电压范围。

公开(公告)号：US08750039B2

公开(公告)日：2014-06-10

申请号：US14023607

申请日：2013-09-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract translation: 存储器包括第一和第二选择栅极晶体管，存储器单元，源极线，位线，连接到作为验证读取的目标的所选存储单元的选定字线，连接的未选择字线 到除所选存储单元之外的未选择的存储单元，用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路， 以及控制电路，其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个，将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。

公开(公告)号：US08743624B2

公开(公告)日：2014-06-03

申请号：US13456005

申请日：2012-04-25

Applicant: Jeffrey W. Lutze ,  Yan Li

Inventor： Jeffrey W. Lutze ,  Yan Li

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418

Abstract: A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.

Abstract translation: 非易失性存储系统对多个非易失性存储元件执行编程，并且有选择地执行应该保持擦除的非易失性存储元件的至少一个子集的重新擦除，而无需有意地擦除编程数据。

公开(公告)号：US20140119139A1

公开(公告)日：2014-05-01

申请号：US14037582

申请日：2013-09-26

Applicant: SAMSUNG ELECTONICS CO., LTD.

Inventor： IL HAN PARK ,  SEUNG-BUM KIM

IPC: G11C16/34 ,  G11C7/00

CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3436 ,  G11C16/344

Abstract: A nonvolatile memory device includes a memory cell array and control logic. The memory cell array includes multiple memory blocks, each memory block including memory cells connected to word lines and bit lines. The control logic is configured to perform an erase operation in which an erase voltage is applied to a memory block of the multiple memory blocks to erase the memory cells of the memory block, and in which an erase verification voltage is applied a selected word line of the memory block to verify respective erase states of memory cells connected to the selected word line. The control logic is further configured to apply a read voltage to the selected word line to extract erase state information of the memory cells, and to control a level of the erase verification voltage based on the erase state information.

Abstract translation: 非易失性存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括多个存储块，每个存储块包括连接到字线和位线的存储器单元。 控制逻辑被配置为执行擦除操作，其中擦除电压被施加到多个存储块的存储块以擦除存储块的存储单元，并且其中擦除验证电压被施加到所选择的字线 所述存储块用于验证连接到所选字线的存储单元的相应擦除状态。 控制逻辑还被配置为向所选字线施加读取电压以提取存储器单元的擦除状态信息，并且基于擦除状态信息来控制擦除验证电压的电平。

公开(公告)号：US20140108705A1

公开(公告)日：2014-04-17

申请号：US13829579

申请日：2013-03-14

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Sergey Anatolievich Gorobets

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0868 ,  G06F2212/222 ,  G06F2212/311 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3431 ,  G11C2211/5641 ,  G11C2211/5643 ,  G11C2211/565

Abstract: A high endurance, short retention NAND memory is used as a read cache for a memory of a higher level of non-volatility, such as standard NAND flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache NAND to accelerate host reads. This may also reduce host's DRAM requirements. In some arrangements, special commands or partitions can be used by operating system to identify these fast read areas. The main non-volatile memory will typically also maintain a back-up copy of data in the cache NAND. In some embodiments, the read cache can be implemented as a middle layer between the host and storage system, say as an SATA-SATA bridge dongle to boost read access for frequently read data or specific patterns, such as a boot sequence.

Abstract translation: 使用高耐久性，短保留NAND存储器作为高级非易失性存储器的读缓存，例如标准NAND闪存或硬盘驱动器。 组合的存储器系统识别主要非易失性存储器或特定读取序列的频繁读取的逻辑地址，并将相应的数据存储在高速缓存NAND中以加速主机读取。 这也可能会降低主机的DRAM要求。 在某些布置中，操作系统可以使用特殊的命令或分区来识别这些快速读取区域。 主要的非易失性存储器通常还将保持缓存NAND中的数据的备份副本。 在一些实施例中，读取的高速缓存可以被实现为主机和存储系统之间的中间层，例如作为SATA-SATA网桥加密狗，以提高频繁读取数据或特定模式（例如引导顺序）的读取访问。

公开(公告)号：US20140082460A1

公开(公告)日：2014-03-20

申请号：US13997212

申请日：2011-12-29

Applicant: Kiran Pangal ,  Ravi J. Kumar

Inventor： Kiran Pangal ,  Ravi J. Kumar

IPC: G06F11/10

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了提供动态窗口以提高NAND（Not And）存储器耐久性的方法和装置。 在一个实施例中，与NAND存储器件相关联的编程擦除窗口通过从较高的擦除验证（TEV）电压开始并基于当前周期在NAND存储器件的使用寿命内随后的周期降低TEV电压而动态地改变 计数值。 或者，通过以更高的擦除验证（PV）电压和擦除验证（TEV）电压开始，并且基于当前的NAND存储器件的使用寿命期间的随后的周期来降低PV和TEV电压，编程擦除窗口被动态变化 循环计数值。 还公开并要求保护其他实施例。

公开(公告)号：US08582363B2

公开(公告)日：2013-11-12

申请号：US12931395

申请日：2011-01-31

Applicant: Peter Wung Lee

Inventor： Peter Wung Lee

IPC: G11C11/34

CPC classification number: G11C16/3409 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0458 ,  G11C16/08 ,  G11C16/24 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Abstract translation: 一种用于通过擦除双电荷保持晶体管NOR闪存单元来设置其阈值电压电平来操作双电荷保持晶体管NOR闪存单元的阵列块的方法和装置，以防止在读取操作期间漏电流损坏数据。 NOR闪存单元的阵列块的擦除通过选择阵列块的块部分中的一个并且强烈且深入擦除，过擦除验证和迭代地编程，直到电荷保持晶体管的阈值电压在较低的电压极限和 第一程序状态的上限电压。 迭代地选择和擦除其他块部分，过度擦除验证，并重复编程，直到电荷保持晶体管的阈值电压在第一编程状态的较低电压限制和上限电压之间，直到整个块被擦除并重新编程 达到正阈值水平。

公开(公告)号：US20130246895A1

公开(公告)日：2013-09-19

申请号：US13421578

申请日：2012-03-15

Applicant: Christophe Laurent ,  Paolo Amato ,  Richard Fackenthal

Inventor： Christophe Laurent ,  Paolo Amato ,  Richard Fackenthal

IPC: H03M13/09 ,  G06F11/10

CPC classification number: G06F11/1072 ,  G06F11/1012 ,  G11C11/56 ,  G11C11/5635 ,  G11C16/107 ,  G11C2029/0411 ,  G11C2211/5641 ,  H03M13/19

Abstract: Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first group of memory cells stores multiple digits of program data per memory cell. The second group of memory cells stores a parity symbol per memory cell. Other apparatuses and/or methods are disclosed.

Abstract translation: 本文公开的主题涉及方法和/或装置，例如包括第一组和第二组存储器单元的装置。 第一组存储单元存储每个存储单元的多个数字的程序数据。 第二组存储器单元存储每个存储单元的奇偶校验符号。 公开了其他装置和/或方法。