公开(公告)号：US20230207045A1

公开(公告)日：2023-06-29

申请号：US17724963

申请日：2022-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yuan-Jen Lee ,  Tien-Wei Chiang ,  Yi-Chun Shih

IPC: G11C29/52 ,  G11C11/16 ,  G06F11/10

CPC classification number: G11C29/52 ,  G06F11/1044 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  H01L27/228

Abstract: A magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array comprising a plurality of memory cells configured to store memory data and a reference MTJ array comprising a plurality of reference cells having MTJ structures. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a gross resistance of the reference MTJ array being related to a strength of an external magnetic field, determine whether the external magnetic field is fatal based on the received gross resistance of the reference MTJ array and a pre-determined threshold, and provide notification indicating that the memory data stored in the main MTJ array is untrustworthy if it is determined that the external magnetic field around the MRAM device is fatal.

公开(公告)号：US11690298B2

公开(公告)日：2023-06-27

申请号：US17453448

申请日：2021-11-03

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Dan Yu

IPC: H01L43/08 ,  G11C11/16 ,  H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  G11C11/1675 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: Magnetic memory structure and memory device are provided. A magnetic memory structure includes a metal layer, a first magnetic tunnel junction, and a second magnetic tunnel junction. The metal layer includes a first contact region and a second contact region. Electrical resistivity of at least a first part of the first contact region is different than electrical resistivity of the second contact region. The first magnetic tunnel junction is disposed on the metal layer. The first magnetic tunnel junction includes a first free layer in contact with the first contact region of the metal layer. The second magnetic tunnel junction is disposed on the metal layer. The second magnetic tunnel junction includes a second free layer in contact with the second contact region of the metal layer.

公开(公告)号：US11688539B2

公开(公告)日：2023-06-27

申请号：US17533044

申请日：2021-11-22

Applicant: University of Pittsburgh—Of the Commonwealth System of Higher Education

Inventor： Jeremy Levy ,  Feng Bi ,  Patrick R. Irvin

IPC: H01F13/00 ,  G11C11/16 ,  G11C11/155 ,  H01F1/40 ,  H01F10/06 ,  H01F10/32 ,  H01F10/193

CPC classification number: H01F13/00 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01F1/40 ,  H01F10/06 ,  H01F10/193 ,  H01F10/3213

Abstract: A structure includes an electronically controllable ferromagnetic oxide structure that includes at least three layers. The first layer comprises STO. The second layer has a thickness of at least about 3 unit cells, said thickness being in a direction substantially perpendicular to the interface between the first and second layers. The third layer is in contact with either the first layer or the second layer or both, and is capable of altering the charge carrier density at the interface between the first layer and the second layer. The interface between the first and second layers is capable of exhibiting electronically controlled ferromagnetism.

公开(公告)号：US20230200256A1

公开(公告)日：2023-06-22

申请号：US18108003

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US11678586B2

公开(公告)日：2023-06-13

申请号：US13737897

申请日：2013-01-09

Applicant: Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Roger Klas Malmhall ,  Ioan Tudosa ,  Rajiv Yadav Ranjan

Inventor： Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Roger Klas Malmhall ,  Ioan Tudosa ,  Rajiv Yadav Ranjan

IPC: H10N50/80 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10N50/01 ,  H10N50/10 ,  Y10T428/1107 ,  Y10T428/1114

Abstract: A spin-transfer torque magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL. The second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL.

公开(公告)号：US20230180621A1

公开(公告)日：2023-06-08

申请号：US17457565

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Tao Li ,  Tsung-Sheng Kang ,  Alexander Reznicek ,  Chih-Chao Yang

IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22 ,  H01L23/522

CPC classification number: H01L43/08 ,  H01L43/10 ,  G11C11/161 ,  H01L43/12 ,  H01L43/02 ,  H01L27/222 ,  H01L23/5226

Abstract: A magneto-resistive random access memory device includes a top electrode electrically connected to a conductive interconnect through a metal capping layer located above a top surface and opposite sidewalls of the top electrode, the conductive interconnect is located on opposite sidewalls of the metal capping layer with a top surface of the metal capping layer being coplanar with a top surface of the conductive interconnect.

公开(公告)号：US20230178129A1

公开(公告)日：2023-06-08

申请号：US17541401

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

CPC classification number: G11C11/161 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L27/222

Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

公开(公告)号：US11665977B2

公开(公告)日：2023-05-30

申请号：US16887244

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Feng Yin ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  H01L27/228 ,  H01L43/12

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

公开(公告)号：US11665970B2

公开(公告)日：2023-05-30

申请号：US17337768

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Whan-Kyun Kim ,  Deok-Hyeon Kang ,  Woo-Jin Kim ,  Woo-Chang Lim ,  Jun-Ho Jeong

IPC: G11C11/16 ,  H01L43/12 ,  H01F41/32 ,  H01L27/22 ,  H01F10/32 ,  H01L43/02 ,  H01F41/30 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01F41/32 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

公开(公告)号：US20230165159A1

公开(公告)日：2023-05-25

申请号：US18058010

申请日：2022-11-22

Applicant: IMEC VZW

Inventor： Jose Diogo Costa ,  Sebastien Couet ,  Geoffrey Pourtois ,  Benoit Van Troeye

IPC: H10N50/10 ,  G11C11/16 ,  H10N50/80

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02

Abstract: The disclosure relates to spin orbit torque (SOT) magnetic random access (MRAM) devices. A magnetic structure for a SOT-MRAM device and a method for fabricating the magnetic structure are presented. The magnetic structure comprises a SOT layer and a magnetic tunnel junction (MTJ) structure arranged on the SOT layer. The SOT layer comprises a material combination of a bismuth-based material and a metal having a melting point of at least 1000° C. As a result, the SOT is thermally stable and also shows a large spin Hall angle (SHA).