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公开(公告)号:US20240338261A1
公开(公告)日:2024-10-10
申请号:US18749220
申请日:2024-06-20
申请人: NVIDIA Corporation
CPC分类号: G06F9/54 , G06F8/311 , G06F9/4494 , G06F9/543
摘要: Apparatuses, systems, and techniques to identify a location of one or more portions of incomplete graph code. In at least one embodiment, a location of one or more portions of incomplete graph code is identified based on, for example, CUDA or other parallel computing platform code.
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公开(公告)号:US20240338235A1
公开(公告)日:2024-10-10
申请号:US18748889
申请日:2024-06-20
申请人: Google LLC
发明人: Craig D. Chambers , Ashish Raniwala , Frances J. Perry , Stephen R. Adams , Robert R. Henry , Robert Bradshaw , Nathan Weizenbaum
IPC分类号: G06F9/455 , G06F8/30 , G06F8/34 , G06F8/41 , G06F9/30 , G06F9/38 , G06F9/44 , G06F9/445 , G06F9/448 , G06F9/48 , G06F16/2453 , G06F21/57 , G06F21/62
CPC分类号: G06F9/45504 , G06F8/314 , G06F8/34 , G06F8/433 , G06F9/38 , G06F9/3851 , G06F9/3885 , G06F9/44 , G06F9/445 , G06F9/45533 , G06F9/4843 , G06F21/577 , G06F21/62 , G06F21/6218 , G06F9/30 , G06F9/4494 , G06F16/24532 , G06F16/24547 , G06F2221/034
摘要: A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.
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公开(公告)号:US12112181B1
公开(公告)日:2024-10-08
申请号:US18701403
申请日:2022-10-18
发明人: Masato Fujino , Jun Kuchii , Yuichiro Takezaki
CPC分类号: G06F9/4494 , H04L63/08
摘要: An information processing system includes a plurality of terminal devices, a client device, and a cloud including one or a plurality of server devices. The client device or the cloud includes: a processing instruction unit for designating a specific terminal device from among the plurality of terminal devices and instructing the specific terminal device to perform processing in accordance with a prescribed program; an authentication information storage unit for retaining authentication information necessary for carrying out the prescribed program; and an authentication information providing unit for providing, to the specific terminal device designated by the processing instruction unit, authentication information or, as a substitute therefor, temporary information, necessary for executing the processing in accordance with the program instructed by the processing instruction unit. The specific terminal device uses the authentication information or the temporary information to execute the processing based on the instruction from the processing instruction unit.
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公开(公告)号:US11966798B2
公开(公告)日:2024-04-23
申请号:US17571359
申请日:2022-01-07
发明人: John Robert Rose , Brian Goetz
IPC分类号: G06F16/00 , G06F8/41 , G06F9/30 , G06F9/445 , G06F9/448 , G06F9/451 , G06F9/455 , G06F9/54 , G06F12/02 , G06F16/22 , G06F16/28
CPC分类号: G06F9/547 , G06F8/41 , G06F8/437 , G06F9/30076 , G06F9/44521 , G06F9/44536 , G06F9/4488 , G06F9/4494 , G06F9/4498 , G06F9/451 , G06F9/45516 , G06F9/541 , G06F9/542 , G06F9/548 , G06F12/023 , G06F16/2272 , G06F16/2291 , G06F16/289
摘要: A type restriction contextually modifies an existing type descriptor. The type restriction is imposed on a data structure to restrict the values that are assumable by the data structure. The type restriction does not cancel or otherwise override the effect of the existing type descriptor on the data structure. Rather the type restriction may declare that a value of the data structure's type is forbidden for the data structure. Additionally or alternatively, the type restriction may declare that an element count allowable for a data structure's type is forbidden for the data structure. Type restriction allows optionality (where only a singleton value for a data structure is allowed), empty sets (where no value for a data structure is allowed), and multiplicity (where only a limited element count for a data structure) to be injected into a code set independent of data type. Type restriction allows certain optimizations to be performed.
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公开(公告)号:US11922238B2
公开(公告)日:2024-03-05
申请号:US17571353
申请日:2022-01-07
发明人: John Robert Rose , Brian Goetz
IPC分类号: G06F9/54 , G06F8/41 , G06F9/30 , G06F9/445 , G06F9/448 , G06F9/451 , G06F9/455 , G06F12/02 , G06F16/22 , G06F16/28
CPC分类号: G06F9/547 , G06F8/41 , G06F8/437 , G06F9/30076 , G06F9/44521 , G06F9/44536 , G06F9/4488 , G06F9/4494 , G06F9/4498 , G06F9/451 , G06F9/45516 , G06F9/541 , G06F9/542 , G06F9/548 , G06F12/023 , G06F16/2272 , G06F16/2291 , G06F16/289
摘要: A parametric constant resolves to different values in different contexts, but a single value within a particular context. An anchor constant is a parametric constant that allows for a degree of parametricity for an API point. The context for the anchor constant is provided by a caller to the API point. The anchor constant resolves to an anchor value that records specialization decisions for the API point within the provided context. Specialization decisions may include type restrictions, memory layout, and/or memory size. The anchor value together with an unspecialized type of the API point result in a specialized type of the API point. A class object representing the specialized type is created. The class object may be accessible to the caller, but the full value of the anchor value is not accessible to the caller. The API point is executed based on the specialization decisions embodied in the anchor value.
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公开(公告)号:US11875160B1
公开(公告)日:2024-01-16
申请号:US17882074
申请日:2022-08-05
发明人: Kilian Grefen
IPC分类号: G06F9/448
CPC分类号: G06F9/4498 , G06F9/4494
摘要: The present invention aims at providing an approach to digital twin-based process control for efficient and accurate achievement of process objectives. Heretofore, a controller service module (18) runs an event-driven control process in a digital twin domain for control of process entities operated in a process domain. The behavior of process entities is modeled through execution of state machine models. Event data is communicated asynchronously to the controller service module (18) for storage in a process cycle buffer (26). A model-based process controller (24) reads input information in processing cycles and controls process entities by operating state machine models to reflect the input of event data. It is checked whether the operation of state machine models triggers the generation of external control commands which are then output by an outbound interface (32) to process entities for control processing.
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公开(公告)号:US11853794B2
公开(公告)日:2023-12-26
申请号:US17937097
申请日:2022-09-30
发明人: Kaan Tekelioglu
CPC分类号: G06F9/4881 , G05B15/02 , G06F8/433 , G06F9/3838 , G06F9/4494 , G06F9/451 , G06F9/5072 , G06F2209/486
摘要: A pipeline task verification method and system is disclosed, and may use one or more processors. The method may comprise providing a data processing pipeline specification, wherein the data processing pipeline specification defines a plurality of data elements of a data processing pipeline. The method may further comprise identifying from the data processing pipeline specification one or more tasks defining a relationship between a first data element and a second data element. The method may further comprise receiving for a given task one or more data processing elements intended to receive the first data element and to produce the second data element. The method may further comprise verifying that the received one or more data processing elements receive the first data element and produce the second data element according to the defined relationship.
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公开(公告)号:US11853244B2
公开(公告)日:2023-12-26
申请号:US15416670
申请日:2017-01-26
IPC分类号: G06F9/38 , G06F15/78 , G06F13/40 , G06F13/16 , G06F9/30 , G06F9/448 , G06F15/76 , G06F9/345 , G06F15/82
CPC分类号: G06F13/4022 , G06F9/30087 , G06F9/3455 , G06F9/3834 , G06F9/3877 , G06F9/4494 , G06F13/1689 , G06F15/76 , G06F15/7889 , G06F15/825
摘要: A reconfigurable hardware accelerator for computers combines a high-speed dataflow processor, having programmable functional units rapidly reconfigured in a network of programmable switches, with a stream processor that may autonomously access memory in predefined access patterns after receiving simple stream instructions. The result is a compact, high-speed processor that may exploit parallelism associated with many application-specific programs susceptible to acceleration.
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公开(公告)号:US11843691B2
公开(公告)日:2023-12-12
申请号:US17344253
申请日:2021-06-10
申请人: Intel Corporation
发明人: Thomas E. Willis , Brad Burres , Amit Kumar
IPC分类号: G06F3/06 , H04L9/08 , G06F9/50 , H04L69/12 , H04L69/32 , G06F16/25 , G06F16/2453 , H04L49/9005 , G11C8/12 , G11C29/02 , H04L41/0896 , G06F30/34 , B25J15/00 , G06F1/18 , G06F1/20 , G06F11/34 , G06F15/78 , H04L41/5025 , H04L67/1008 , H05K7/14 , H05K7/18 , H05K7/20 , H04L67/1001 , G11C29/36 , G11C29/38 , G11C29/44 , G06F16/22 , G06F16/2455 , G06F12/02 , G06F12/14 , G06F13/16 , G06F15/173 , G06F13/40 , G06F13/42 , G06F9/448 , G06F9/28 , G06F15/16 , H04L41/0893 , H04L69/22 , H04L69/321 , H04L41/0213 , H04L41/0668 , H04L41/0677 , H04L45/28 , H04L45/7453 , H04L47/11 , H04L47/125 , H04L49/00 , H04L49/351 , G06F9/4401 , G06F9/445 , G06F12/06 , G06F16/23 , G06F16/248 , G06F16/901 , G06F16/11 , G06F9/44 , G06F9/48 , G06F21/10 , G06N3/063 , G06Q10/0631 , G06Q30/0283 , H04L41/14 , H04L41/5019 , H04L49/40 , H04L9/40 , G06F12/0802 , G06F12/1045
CPC分类号: H04L9/0819 , B25J15/0014 , G06F1/183 , G06F1/20 , G06F3/0604 , G06F3/065 , G06F3/0605 , G06F3/067 , G06F3/0611 , G06F3/0613 , G06F3/0629 , G06F3/0631 , G06F3/0632 , G06F3/0644 , G06F3/0647 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F3/0685 , G06F9/28 , G06F9/445 , G06F9/4406 , G06F9/4411 , G06F9/4494 , G06F9/505 , G06F9/5044 , G06F9/5088 , G06F11/3442 , G06F12/023 , G06F12/06 , G06F12/0607 , G06F12/14 , G06F13/1663 , G06F13/1668 , G06F13/4068 , G06F13/42 , G06F15/161 , G06F15/17331 , G06F15/7807 , G06F15/7867 , G06F16/119 , G06F16/221 , G06F16/2237 , G06F16/2255 , G06F16/2282 , G06F16/2365 , G06F16/248 , G06F16/2453 , G06F16/2455 , G06F16/24553 , G06F16/25 , G06F16/9014 , G06F30/34 , G11C8/12 , G11C29/028 , G11C29/36 , G11C29/38 , G11C29/44 , H04L9/0894 , H04L41/0213 , H04L41/0668 , H04L41/0677 , H04L41/0893 , H04L41/0896 , H04L41/5025 , H04L45/28 , H04L45/7453 , H04L47/11 , H04L47/125 , H04L49/30 , H04L49/351 , H04L49/9005 , H04L67/1001 , H04L67/1008 , H04L69/12 , H04L69/22 , H04L69/32 , H04L69/321 , H05K7/1489 , H05K7/18 , H05K7/20209 , H05K7/20736 , G06F9/44 , G06F9/4401 , G06F9/4856 , G06F9/5061 , G06F12/0802 , G06F12/1054 , G06F12/1063 , G06F13/4022 , G06F15/1735 , G06F21/105 , G06F2200/201 , G06F2201/85 , G06F2209/509 , G06F2212/1044 , G06F2212/1052 , G06F2212/601 , G06F2213/0026 , G06F2213/0064 , G06F2213/3808 , G06N3/063 , G06Q10/0631 , G06Q30/0283 , H04L41/14 , H04L41/5019 , H04L49/40 , H04L63/0428 , H05K7/1498
摘要: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.
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公开(公告)号:US11836552B2
公开(公告)日:2023-12-05
申请号:US17571379
申请日:2022-01-07
发明人: John Robert Rose , Brian Goetz
IPC分类号: G06F9/44 , G06F9/54 , G06F8/41 , G06F16/28 , G06F16/22 , G06F9/448 , G06F9/445 , G06F9/30 , G06F9/451 , G06F12/02 , G06F9/455
CPC分类号: G06F9/547 , G06F8/41 , G06F8/437 , G06F9/30076 , G06F9/4488 , G06F9/4494 , G06F9/4498 , G06F9/44521 , G06F9/44536 , G06F9/451 , G06F9/45516 , G06F9/541 , G06F9/542 , G06F9/548 , G06F12/023 , G06F16/2272 , G06F16/2291 , G06F16/289
摘要: A type restriction contextually modifies an existing type descriptor. The type restriction is imposed on a data structure to restrict the values that are assumable by the data structure. The type restriction does not cancel or otherwise override the effect of the existing type descriptor on the data structure. Rather the type restriction may declare that a value of the data structure's type is forbidden for the data structure. Additionally or alternatively, the type restriction may declare that an element count allowable for a data structure's type is forbidden for the data structure. Type restriction allows optionality (where only a singleton value for a data structure is allowed), empty sets (where no value for a data structure is allowed), and multiplicity (where only a limited element count for a data structure) to be injected into a code set independent of data type. Type restriction allows certain optimizations to be performed.
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