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    LOG-STRUCTURED FILED SYSTEM WITH FILE BRANCHING
    92.
    发明申请
    LOG-STRUCTURED FILED SYSTEM WITH FILE BRANCHING 有权

    公开(公告)号：US20150347288A1

    公开(公告)日：2015-12-03

    申请号：US14292089

    申请日：2014-05-30

    Applicant: SolidFire, Inc.

    Inventor： Bill Minckler ,  David D. Wright

    IPC: G06F12/02 ,  G06F3/06

    CPC classification number: G06F12/0238 ,  G06F3/0616 ,  G06F3/0626 ,  G06F3/0643 ,  G06F3/0679 ,  G06F17/30091 ,  G06F17/30185 ,  G06F2212/1056 ,  G06F2212/202 ,  G06F2212/214

    Abstract: Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is determined based upon the sequence numbers and a checkpoint file is read within the latest region. A request for a block of data of a first branch is received. A first block of pointers associated with the first branch from the checkpoint file is read. A first pointer from the first block of pointers and a second block of pointers pointed to by the first pointer are read. A second pointer from the second block of pointers and a third block of pointers pointed to by the second pointer are read. A third pointer from the third block of pointers and data pointed to by the third pointer are read. The block of data of the first branch is determined based upon the read data. The block of data is returned.

    STORAGE SUBSYSTEM AND METHOD FOR CONTROLLING THE SAME
    93.
    发明申请
    STORAGE SUBSYSTEM AND METHOD FOR CONTROLLING THE SAME 有权
    存储子系统及其控制方法

    公开(公告)号：US20150342095A1

    公开(公告)日：2015-11-26

    申请号：US14376329

    申请日：2013-12-11

    Applicant: HITACHI, LTD.

    Inventor： Shigeaki TANAKA ,  Takashi CHIKUSA

    IPC: H05K7/20

    CPC classification number: H05K7/20736 ,  G06F1/20 ,  G06F3/06 ,  G06F3/0658 ,  G06F3/0689 ,  G06F11/108 ,  G06F12/08 ,  G06F12/0868 ,  G06F2212/214 ,  G11B33/124

    Abstract: The present invention aims at providing a storage subsystem capable of improving a backend-side I/O processing performance and enabling a single semiconductor memory adapter to be replaced at a time. Therefore, the present invention provides one or more semiconductor memory adapter boards mounting semiconductor memories each having smaller capacity than SSDs attached detachably to a drive canister, a wide port connection established to access the semiconductor memories, the semiconductor memories used as a read cache area of HDDs, and further adopts a wind direction control structure for ensuring a cooling wind path to the HDDs when an adapter board is attached.

    Abstract translation: 本发明旨在提供一种能够提高后端侧I / O处理性能并且能够一次更换单个半导体存储器适配器的存储子系统。 因此，本发明提供了一个或多个安装半导体存储器的半导体存储器适配器板，每个半导体存储器的容量比可拆卸地附接到驱动罐的SSD容量小，建立用于访问半导体存储器的宽端口连接，用作读取高速缓存区域的半导体存储器 并且当安装适配器板时，还采用风向控制结构来确保到HDD的冷却风路。

    STORAGE SYSTEM AND DATA BACKUP METHOD
    95.
    发明申请
    STORAGE SYSTEM AND DATA BACKUP METHOD 有权
    存储系统和数据备份方法

    公开(公告)号：US20150293714A1

    公开(公告)日：2015-10-15

    申请号：US14234017

    申请日：2013-05-30

    Applicant: Hitachi, Ltd.

    Inventor： Ryosuke Matsubara ,  Hiroki Kanai ,  Toru Maeda

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0685 ,  G06F11/1441 ,  G06F11/2015 ,  G06F11/2089 ,  G06F11/3034 ,  G06F11/3058 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/124 ,  G06F2003/0691 ,  G06F2212/214 ,  Y02D10/13 ,  Y02D10/14

    Abstract: A storage system which is connected to a host computer, includes a storage device; a first controller which controls data transfers between the storage device and the host computer; a second controller connected to the first controller and controls data transfers between the storage device and the host computer; a non-volatile memory; and a battery device. The first controller includes a first volatile memory and the second controller comprising a second volatile memory. Upon a power outage, the battery device starts supplying electric power to the first controller and the second controller, and wherein the second controller copies data which is stored in the first volatile memory to the second volatile memory and, after copying is complete, stops operation of the first controller, stops the power supply from the battery device to the first controller, and copies data.

    Abstract translation: 连接到主计算机的存储系统包括存储装置; 第一控制器，用于控制存储设备和主计算机之间的数据传输; 连接到第一控制器的第二控制器，控制存储设备和主机之间的数据传输; 非易失性存储器; 和电池装置。 第一控制器包括第一易失性存储器，第二控制器包括第二易失性存储器。 在停电时，电池装置开始向第一控制器和第二控制器供电，并且其中第二控制器将存储在第一易失性存储器中的数据复制到第二易失性存储器，并且在复制完成之后停止操作 的第一个控制器，停止从电池设备到第一个控制器的电源，并复制数据。

    SEMICONDUCTOR MEMORY DEVICE
    97.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20150262630A1

    公开(公告)日：2015-09-17

    申请号：US14475493

    申请日：2014-09-02

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Masanobu SHIRAKAWA ,  Tokumasa HARA

    IPC: G11C7/10 ,  G11C7/24 ,  G06F12/08

    CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0875 ,  G06F13/16 ,  G06F2212/1016 ,  G06F2212/214 ,  G06F2212/452 ,  G06F2212/7203 ,  G06F2212/7207 ,  G11C7/1063 ,  G11C7/24 ,  G11C16/10 ,  G11C16/26

    Abstract: A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.

    Abstract translation: 存储器件包括第一和第二存储单元阵列，以及控制电路，被配置为输出指示第一存储单元阵列是否处于就绪状态的第一信息，其中控制电路准备好接收访问第一存储单元阵列的命令 或控制电路未准备好接收访问第一存储单元阵列的命令的忙状态，以及指示第二存储单元阵列是否处于就绪状态的第二信息，其中控制电路准备好接收命令 以访问第二存储器单元阵列或其中控制电路未准备好接收用于访问第二存储单元阵列的命令的忙状态。

    Method and system for distributing tiered cache processing across multiple processors
    99.
    发明授权
    Method and system for distributing tiered cache processing across multiple processors 有权
    跨多个处理器分层分层缓存处理的方法和系统

    公开(公告)号：US09122606B2

    公开(公告)日：2015-09-01

    申请号：US13300804

    申请日：2011-11-21

    Applicant: Kapil Sundrani

    Inventor： Kapil Sundrani

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0804 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0875 ,  G06F2212/214

    Abstract: A data storage system having at least one cache and at least two processors balances the load of data access operations by directing certain processes in each data access operation to one of the processors. Each processor may be optimized for its specific processes. One processor may be dedicated to receiving and servicing data access requests; another processor may be dedicated to background tasks and cache management.

    Abstract translation: 具有至少一个高速缓存的数据存储系统和至少两个处理器通过将每个数据访问操作中的某些进程指向一个处理器来平衡数据访问操作的负载。 每个处理器可以针对其特定过程进行优化。 一个处理器可以专用于接收和服务数据访问请求; 另一个处理器可能专门用于后台任务和缓存管理。

    Systems and methods for identifying and compressing rarely used data
    100.
    发明授权
    Systems and methods for identifying and compressing rarely used data 有权
    用于识别和压缩很少使用的数据的系统和方法

    公开(公告)号：US09110857B1

    公开(公告)日：2015-08-18

    申请号：US14288992

    申请日：2014-05-28

    Applicant: SanDisk Technologies Inc.

    Inventor： Tal Rostoker ,  Alon Marcu

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G11C7/10 ,  G06F3/06 ,  G06F12/02 ,  H01L27/06

    CPC classification number: G06F13/1657 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/1689 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/401 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/06 ,  G11C2207/102 ,  H01L27/0688

    Abstract: Systems and methods are disclosed for identifying and compressing rarely used data. A storage module may include a memory and a storage controller in operative communication with the memory. The storage controller is configured to identify an access of data stored at a first portion of the memory; determine, based on a first value of the access counter associated with the identified access and a second value of the access counter, that an age of the data stored at the first portion of the memory exceeds a threshold; identify data stored at a second portion of the memory that is associated with a third value of the access counter, where the third value of the access counter is within a range of the first value of the access counter; and compress together at least the data stored at the first and second portions of the memory.

    Abstract translation: 公开了用于识别和压缩很少使用的数据的系统和方法。 存储模块可以包括与存储器可操作地通信的存储器和存储控制器。 存储控制器被配置为识别存储在存储器的第一部分的数据的访问; 基于与所识别的访问相关联的访问计数器的第一值和访问计数器的第二值确定存储在存储器的第一部分的数据的年龄超过阈值; 识别存储在存储器的与存取计数器的第三值相关联的第二部分的数据，其中访问计数器的第三值在访问计数器的第一值的范围内; 并且至少压缩存储在存储器的第一和第二部分的数据。

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